ADP5138ACPZ-2-R7 datasheet(9/23 Pages) AD

部件名	ADP5138ACPZ-2-R7

功能描述	Quad, 1 A, 5.5 V, Synchronous Step-Down Regulators with One RF LDO Regulator

PDF	23 Pages

Scroll/Zoom	100%

制造商	AD [Analog Devices]

网页	http://www.analog.com

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9 / 23 page

Data Sheet

ADP5138

Rev. A | Page 9 of 23

Pin No.

Mnemonic

Description

GND

Analog Ground. Connect this pin to the ground plane.

SYNC

Synchronization Input. Connect this pin to an external clock between 2.8 MHz and 3.5 MHz to synchronize the

switching frequency to the external clock. If synchronization function is not used, connect this pin to GND.

AVIN

Bias Voltage Input Pin. Connect AVIN to PVINx, and connect a bypass capacitor between AVIN and GND.

EN1

Precision Enable Pin for Channel 1. Use an external resistor divider to set the turn-on threshold. To enable

Channel 1 automatically, connect the EN1 pin to PVIN1.

FB1

Feedback Voltage Sense Input for Channel 1. Connect this pin to a resistor divider from VOUT1 for the adjustable

version. For the fixed output version, connect this pin to VOUT1 directly.

Exposed Pad. Solder the exposed pad to an external ground plane.

ADP5138ACPZ-2-R7 数据表(PDF) 9 Page - Analog Devices