ADP5138

Data Sheet

Rev. A | Page 18 of 23

POWER-ON RESET (POR)

The ADP5138 integrates the POR circuit to monitor the input

voltage and output voltage of the regulators. The POR pin is an

active high, open-drain output that requires a resistor to pull

the pin up to a voltage.

The ENx pin voltage determines which output voltage is

monitored in the POR circuit. When the ENx pin voltage

exceeds 1.2 V (typical), the POR circuit monitors the

corresponding output voltage. When the ENx pin voltage is

lower than 1.1 V (typical), the POR circuit does not monitor

the corresponding output voltage.

The POR pin does not pull high until all of the following

conditions are met followed by a 5.7 ms (typical) delay:

•

The input voltage is greater than the undervoltage lockout

threshold and undervoltage monitor threshold.

•

The input voltage is less than the input overvoltage

threshold.

•

No thermal shutdown.

•

All the power-good signals are high for these monitored

output voltages.

The POR pin is pulled down when any of these conditions are

not met with a 10 µs deglitch time.

If all the channels are disabled, the POR pin pulls down to

ground.

The POR output is fully controlled when the voltage on AVIN is

SOFT START AND POWER-UP SEQUENCE

The ADP5138 has integrated soft start circuitry for each channel

to limit the output voltage rising time and to reduce the inrush

current during startup. The soft start time is fixed at 500 µs

(typical) for the buck regulators and 570 µs (typical) for the

LDO regulator.

When the ADP5138 exits the input UVLO, input OVLO, or

thermal shutdown event, there is a fixed delay time on each

enable signal. This delay time prevents all the regulators from

powering up at the same time and reduces the input inrush

current. Table 7 shows the delay time for each channel.

Table 7. Enable Delay Time for Each Channel

Channel

Delay Time

Channel 1

15 µs

Channel 2

Channel 3

Channel 4

Channel 5

Figure 46 shows the power-up sequence when the ENx pins are

pulled up at the same time. Channel 1 powers up first, followed

by Channel 2, Channel 3, Channel 4, and Channel 5.

Figure 47 shows the power-up sequence when the channels are

enabled at different times.

Figure 46. Power-Up Sequence with All Channels Enabled at Same Time

Figure 47. Power-Up Sequence with Channels Enabled at Different Times

CURRENT-LIMIT AND SHORT-CIRCUIT

PROTECTION

The ADP5138 integrates a cycle by cycle, peak current-limit

protection circuit to prevent current runaway for each buck

regulator. The high-side FET peak current is limited to 1.6 A

(typical). When the peak inductor current reaches the current-

limit threshold, the high-side FET turns off, the low-side FET

turns on, and the output reference voltage decreases.

The low-side FET in the buck regulator can also sink current

from the load. If the low-side sink current limit is exceeded, both

the low-side and high-side FETs are turned off until the next

cycle starts.

ENx

POR

95%

4 ×

3 ×

2 ×

EN2, EN3

EN1, EN4, EN5

POR

3 ×

4 ×

95%

2 ×

95%