Data Sheet

ADP5138

Rev. A | Page 17 of 23

THEORY OF OPERATION

The ADP5138 is a power management IC that integrates four

buck regulators and one low noise LDO in a 28-lead LFCSP

package. The device can operate with a PVINx input voltage

from 3 V to 5.5 V and can regulate the output voltage down to

0.8 V or set by factory. It provides input UVLO, OVLO, and

UVM features. The ADP5138 also monitors the output voltage

and provides the POR output.

CONTROL SCHEME

The ADP5138 uses a fixed frequency, peak current mode,

PWM control architecture. At the start of each oscillator cycle,

the high-side field effect transistor (FET) turns on, placing a

positive voltage across the inductor. The inductor current

increases until the current sense signal crosses the peak

inductor current threshold that turns off the high-side FET and

turns on the low-side FET, which, in turn, places a negative

voltage across the inductor, causing the inductor current to reduce.

The low-side FET stays on for the remainder of the cycle.

PRECISION ENABLE AND SHUTDOWN

The ADP5138 has five independent enable pins (ENx) for each

channel. The ENx pins are precision analog inputs that enable

the regulator when the voltage on ENx exceeds 1.2 V (typical).

When the ENx voltage falls below 1.1 V (typical), the regulator

turns off. An internal pull-down resistor (1 MΩ) prevents the

regulator from being accidentally enabled if ENx is left floating.

To force the ADP5138 to automatically start when the input

power is applied, connect ENx to PVINx.

OSCILLATOR AND PHASE SHIFT

The buck regulators in the ADP5138 run at a 3.2 MHz fixed

switching frequency. For Channel 2 to Channel 4, the phase

shift with respect to Channel 1 is set to 90°, which reduces the

input ripple current and the input capacitance, thereby helping

to lower system EMI.

Figure 45. Even Phase Shift Between Channel 1 and Channel 4

SYNCHRONIZATION

To synchronize the ADP5138, connect an external clock to the

SYNC pin. The external clock frequency can be in the 2.8 MHz

to 3.5 MHz range. During synchronization, Channel 1 runs in

phase with the external clock.

If the synchronization function is not used, connect the SYNC pin

to ground.

INPUT OVERVOLTAGE LOCKOUT (OVLO)

The ADP5138 integrates an input overvoltage lockout circuit on

(typical), an OVLO event is detected, all the regulators are

turned off, and the POR is pulled down to ground. When the

input voltage falls back to 5.72 V (typical) or less, the OVLO

releases and a soft start reinitializes.

INPUT UNDERVOLTAGE MONITOR (UVM)

The ADP5138 integrates an input undervoltage monitoring

below 4.2 V (typical), the POR pin pulls down to ground while

the device still works until the input voltage drops down to the

input voltage UVLO threshold. When the input voltage exceeds

4.28 V (typical), the POR pin pulls high after a POR rising delay

INPUT UNDERVOLTAGE LOCKOUT (UVLO)

The ADP5138 integrates an input undervoltage lockout circuit

2.8 V (typical), an input UVLO event is detected, all the regulators

turn off, and the POR pin pulls down to ground. When the

input voltage recovers from the UVLO event and the input

voltage exceeds 2.9 V (typical), a soft start reinitializes.

OUTPUT VOLTAGE POWER-GOOD

Each of the five regulators integrates an output voltage power-

good monitoring circuit.

When the output voltage drops below the undervoltage falling

threshold (93% of the nominal output voltage), an output under-

voltage event is detected, and the power-good signal becomes

low. When the output voltage rises above the undervoltage

rising threshold (95% of the nominal output voltage), the

power-good signal becomes high.

When the output voltage exceeds the overvoltage rising

threshold (110% of the nominal output voltage), an output

overvoltage event is detected. During the output overvoltage,

the corresponding regulator stops switching, and the power-

good signal becomes low. When the output voltage drops below

the overvoltage falling threshold (108% of the nominal output

voltage), the corresponding regulator recovers to normal

operation, and the power-good signal becomes high.

SW1

SW2

SW3

SW4

90°

90°

90°

90°