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5. Interface Description

5.5. Command Termination

In order to terminate ongoing read and write operations and put the chip into standby mode, CE#

must be pulled high immediately after all read/write operations. Not doing so will block internal re-

fresh operations and cause memory failure.

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Figure 5-1. Write Command Termination

For a memory controller to correctly latch the last piece of data prior to read-termination, it is rec-

data window.

Set Burst

Length

'hC0

S

-

-

-

133/144 Q

-

-

-

133/144

Read ID

'h9F

S

S

0

S

133/144 N/A

Command

Code

SPI Mode (QE=0)

QPI Mode (QE=1)

Cmd

Addr

Wait

Cycle DIO

MAX

Freq.

Cmd

Addr

Wait

Cycle

DIO MAX Freq.

���� Notes*:

1. S=Serial I/O; Q=Quad I/O.

2. 133/144 MHz max without crossing page boundaries, and 84 MHz max when burst commands cross page

boundaries.

3. For ESP-PSRAM64, the maximum frequency is 144 MHz, while for ESP-PSRAM64H it is 133 MHz.

Espressif Systems

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2018.06

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