EDBA164B4PK-1DITF-R datasheet(39/152 Pages) MICRON

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Table 32: MR8 Op-Code Bit Definitions (Continued)

Feature

Type

Definition

Density

Read-only

OP[5:2]

0000b: 64Mb

0001b: 128Mb

0010b: 256Mb

0011b: 512Mb

0100b: 1Gb

0101b: 2Gb

0110b: 4Gb

0111b: 8Gb

1000b: 16Gb

1001b: 32Gb

All others: Reserved

I/O width

Read-only

OP[7:6]

00b: x32

01b: x16

10b: x8

11b: not used

Table 33: MR9 Test Mode (MA[7:0] = 09h)

OP7

OP6

OP5

OP4

OP3

OP2

OP1

OP0

Vendor-specific test mode

Table 34: MR10 Calibration (MA[7:0] = 0Ah)

OP7

OP6

OP5

OP4

OP3

OP2

OP1

OP0

Calibration code

Table 35: MR10 Op-Code Bit Definitions

Notes 1–6 apply to all parameters and conditions

Feature

Type

Definition

Calibration code

Write-only

OP[7:0]

0xFF: Calibration command after initialization

0xAB: Long calibration

0x56: Short calibration

0xC3: ZQRESET

All others: Reserved

Notes:

1. Host processor must not write MR10 with reserved values.

2. The device ignores calibration commands when a reserved value is written into MR10.

3. See AC timing table for the calibration latency.

216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM

Mode Register Definition

09005aef85eb530a

216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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