EDBA164B4PK-1DITF-R datasheet(1/152 Pages) MICRON

部件名	EDBA164B4PK-1DITF-R

功能描述	216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM Features

PDF	152 Pages

Scroll/Zoom	100%

制造商	MICRON [Micron Technology]

网页	http://www.micron.com

标志

1 / 152 page

LPDDR2 SDRAM

EDB8164B4PR, EDB8164B4PK, EDB8164B4PT, EDBA164B2PR

Features

• Ultra-low-voltage core and I/O power supplies

• Frequency range

– 533 MHz (data rate: 1066 Mb/s/pin)

•4n prefetch DDR architecture

• 8 internal banks for concurrent operation

• Multiplexed, double data rate, command/address

inputs; commands entered on each CK_t/CK_c

edge

• Bidirectional/differential data strobe per byte of

data (DQS_t/DQS_c)

• Programmable READ and WRITE latencies (RL/WL)

• Burst length: 4, 8, and 16

• Per-bank refresh for concurrent operation

• Auto temperature-compensated self refresh

(ATCSR) by built-in temperature sensor

• Partial-array self refresh (PASR)

• Deep power-down mode (DPD)

• Selectable output drive strength (DS)

• Clock-stop capability

• Lead-free (RoHS-compliant) and halogen-free

packaging

Table 1: Key Timing Parameters

Speed

Grade

Clock Rate

(MHz)

Data Rate

(Mb/s/pin)

RL

WL

1D

533

1066

8

4

Options

Marking

• Density/Page Size

– 8Gb/2-CS – dual die

81

– 16Gb/4-CS – quad die

A1

• Organization

– x64

64

•VDD1/VDD2/VDDQ: 1.8V/1.2V/1.2V

B

• Revision

– Dual die

4

– Quad die

2

• FBGA “green” package

– 12mm x 12mm x 0.8mm, 216-ball

PoP FBGA package, dual die

PR

– 12mm x 12mm x 0.8mm, 216-ball

PoP FBGA package, dual die

PT

– 12mm x 12mm x 1.0mm, 216-ball

PoP FBGA package, quad die

PR

– 14mm x 14mm x 0.7mm, 220-ball

PoP FBGA package, dual die

PK

• Timing – cycle time

– 1.875ns @ RL = 8

-1D

• Special options

– Non-Automotive

blank

• Operating temperature range

– From –30°C to +85°C

blank

– From –40°C to +85°C

IT

– From –40°C to +105°C

AT

Table 2: S4 Configuration Addressing

Architecture

128 Meg x 64

256 Meg x 64

Die configuration

16 Meg x 32 x 8 banks x 2 channel

32 Meg x 32 x 8 banks x 2 channel

Row addressing

16K A[13:0]

Column addressing

1K A[9:0]

Number of die

2

4

Die per rank

1

2

Ranks per channel

1

2

Note:

1. A channel is a complete LPDRAM interface, including command/address and data pins.

216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM

Features

09005aef85eb530a

216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN

1

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Products and specifications discussed herein are subject to change by Micron without notice.

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