FS8308 datasheet(6/15 Pages) ETC1

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Advance Information

FS8308

Page 6

April 2003

Functional Description

Programmable Input Frequency Divider

The VCO input to the FIN pin is divided by the programmable divider and then internally

output to the phase/frequency detector (PFD) as f

V. The programmable input frequency

divider consists of a ÷ 64/65 (P/P+1) dual-modulus prescaler in prior to a 18-bit (N)

counter, which is further comprised of a 6-bit swallow (A) counter, and a 12-bit main (B)

counter. The total divide ratio, N, is related to values for P, A, and B through the relation

with

The minimum available programmable divisor for continuous counting is

given by

and the valid total divide ratio range for the

input divider is

Take N=10000 for example, since P=64 and hence that B=156 and A=16. Therefore, the

binary codes of B and A should be 0000 1001 1100 and 010000, respectively. An alterna-

tive approach is to translate the decimal N into binary code directly. And then just take the

last 6-bit as A and the remaining 12-bit as B. By far the binary code of N=10000 is

00 0010 0111 0001 0000. One can get the same result as the former method.

Programmable Reference Frequency Divider

The crystal oscillator output is divided by the programmable divider and then internally

output to the PFD as f

R. The programmable reference frequency divider consists of a fixed

÷ 8 (S) prescaler and a 13-bit reference (R) counter. The total divide ratio, T, is related to

values for S and R through the relation

The usable divisior range of the reference counter is

and therefore, the

valid total divide ratio range for the reference divider is

(in steps of

8.)

() AP

B A

–

()

B A.

≥

PP 1

–

()

4032,

4032 to 262143.

TS R

5 to 8191

40 to 65528

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