Advance Information
FS8308
Page 7
April 2003
Serial Input Data Format
The divsors of the input and reference dividers are input using a 20-bit serial interface
consisting of separate clock (CLK), data (DATA), and latch enable (LE) lines. The format
of the serial data is shown in Fig. 1. The data on the DATA line is written to the shift reg-
ister on the rising edge of the CLK signal and is input with MSB first. The last two bits are
recognized as the latch select control bits. Data on the DATA line should be changed on
the falling edge of CLK, and LE should be held low while data is being written to the shift
register. Data is transferred from the shift register to either one of the frequency divider
latches or the optional control latch when LE is set high. When the latch select control bits
are set high-low or low-low, data is loaded to the 18-bit N-counter latch, and when the
latch select control bits are set high-high, the 2 MSBs are ignored, the next 13 data bits are
loaded to the 13-bit R-counter latch and the remaining 3 LSBs are used to control testing
modes and should be set as follows for normal operation: R14 = high, R15 = low, R16 =
low. To disable LD output (i.e. set LD low), R14 should be set low. When the latch select
control bits are set low-high, the 2 MSBs are recognized as PS and SW, which are used as
stand-by control and open drain output control, respectively. The detail of two control bits
setting is summarized in Table 1. In normal work condition, PS is set to low. When PS is
programmed to high, it will enter stand-by mode.
Serial input data timing waveforms are shown in Fig. 2.
Fig. 1 – Serial input data format
Table 1: Control Bit Setting
1st CB
2nd CB
Fetching Target of Serial Data Input
X
0
N-counter
0
1
PS and SW
1
1
R-counter
18-bit data for N-counter
13-bit data for R-counter
ignored
ignored
optionalcontrol
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
