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USB7252P 数据表(PDF) 26 Page - Microchip Technology |
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USB7252P 数据表(HTML) 26 Page - Microchip Technology |
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26 / 64 page ![]() USB7252P DS00003561A-page 26 2018 - 2020 Microchip Technology Inc. 3.4 Physical and Logical Port Mapping The USB72xx family of devices are based upon a common architecture, but all have different modifications and/or pin bond outs to achieve the various device configurations. The base chip is composed of a total of 6 USB3 PHYs and 7 USB2 PHYs. These PHYs are physically arranged on the chip in a certain way, which is referred to as the PHYSICAL port mapping. The actual port numbering is remapped by default in different ways on each device in the family. This changes the way that the ports are numbered from the USB host’s perspective. This is referred to as LOGICAL mapping. The various configuration options available for these devices may, at times, be with respect to PHYSICAL mapping or LOGICAL mapping. Each individual configuration option which has a PHYSICAL or LOGICAL dependency is declared as such within the register description. The PHYSICAL vs. LOGICAL mapping is described for all port related pins in Table 3-7. A system design in schematics and layout is generally performed using the pinout in Section 3.1, Pin Assignments, which is assigned by the default LOGICAL mapping. Hence, it may be necessary to cross reference the PHYSICAL vs. LOGICAL look up tables when determining the hub configuration. PRT_CTL3_U3 O12 Port 3 USB 3.2 PortSplit power enable This signal is an active high control signal used to enable to the USB 3.2 portion of the downstream port 3 when PortSplit is enabled. When PortSplit is disabled, this pin is not used. Note: This signal should only be used to control an embedded USB 3.2 device. Float GPIOx I/O12 General Purpose Input/Output (x = 70-71, 78, 83, 90-92) Weak pull- down to GND Note: The MPLAB Connect tool makes configuration simple; the settings can be selected by the user with respect to the LOGICAL port numbering. The tool handles the necessary linking to the PHYSICAL port settings. Refer to Section 6.0, Device Configuration for additional information. TABLE 3-7: USB7252P PHYSICAL VS. LOGICAL PORT MAPPING Device Pin Pin Name (as in datasheet) LOGICAL PORT NUMBER PHYSICAL PORT NUMBER 0 1 2 3 4 0 1 2 3 4 5 6 5 USB2DN_DP1 X X 6 USB2DN_DM1 X X 7 USB3DN_TXDP1A X X 8 USB3DN_TXDM1A X X 10 USB3DN_RXDP1A X X 11 USB3DN_RXDM1A X X 14 USB2DN_DP4 X X 15 USB2DN_DM4 X X 16 USB3DN_TXDP1B X X 17 USB3DN_TXDM1B X X 19 USB3DN_RXDP1B X X TABLE 3-6: PROGRAMMABLE FUNCTIONS DESCRIPTIONS (CONTINUED) Function Buffer Type Description If Unused |
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