STM32F107VB datasheet(69/108 Pages) STMICROELECTRONICS

部件名	STM32F107VB

功能描述	Connectivity line, ARM®-based 32-bit MCU with 64/256 KB Flash, USB OTG, Ethernet, 10 timers, 2 CANs, 2 ADCs, 14 communication interfaces

PDF	108 Pages

Scroll/Zoom	100%

制造商	STMICROELECTRONICS [STMicroelectronics]

网页	http://www.st.com

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69 / 108 page

DocID15274 Rev 10

69/108

STM32F105xx, STM32F107xx

Electrical characteristics

107

Table 44. I2S characteristics

Symbol

Parameter

Conditions

Min

Max

Unit

fCK

1/tc(CK)

I2S clock frequency

Master data: 16 bits, audio

freq = 48 K

1.52

1.54

MHz

Slave

6.5

tr(CK)

tf(CK)

I2S clock rise and fall time

capacitive load CL = 50 pF

tw(CKH)(1)

I2S clock high time

Master fPCLK = 16 MHz,

audio freq = 48 K

317

320

tw(CKL)(1)

I2S clock low time

333

336

tv(WS) (1)

WS valid time

Master mode

th(WS) (1)

WS hold time

Master mode

I2S2

I2S3

tsu(WS) (1)

WS setup time

Slave mode

I2S2

I2S3

th(WS) (1)

WS hold time

Slave mode

DuCy(SCK)

I2S slave input clock duty

cycle

Slave mode

tsu(SD_MR) (1)

Data input setup time

Master receiver

I2S2

I2S3

tsu(SD_SR) (1)

Slave receiver

I2S2

I2S3

th(SD_MR)(1)

Data input hold time

Master receiver

I2S2

I2S3

th(SD_SR) (1)

Slave receiver

I2S2

I2S3

tv(SD_ST) (1)(3) Data output valid time

Slave transmitter

(after enable edge)

I2S2

I2S3

th(SD_ST) (1)

Data output hold time

Slave transmitter

(after enable edge)

I2S2

I2S3

tv(SD_MT) (1)

Data output valid time

Master transmitter

(after enable edge)

I2S2

I2S3

th(SD_MT) (1)

Data output hold time

Master transmitter

(after enable edge)

I2S2

I2S3

1. Based on design simulation and/or characterization results, not tested in production.

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