STM32F107VB datasheet(7/108 Pages) STMICROELECTRONICS

7 / 108 page

DocID15274 Rev 10

7/108

STM32F105xx, STM32F107xx

List of figures

Figure 1.

STM32F105xx and STM32F107xx connectivity line block diagram . . . . . . . . . . . . . . . . . 13

Figure 2.

STM32F105xx and STM32F107xx connectivity line BGA100 ballout top view . . . . . . . . . 24

Figure 3.

STM32F105xx and STM32F107xx connectivity line LQFP100 pinout . . . . . . . . . . . . . . . . 25

Figure 4.

STM32F105xx and STM32F107xx connectivity line LQFP64 pinout . . . . . . . . . . . . . . . . . 26

Figure 5.

Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 6.

Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 7.

Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 8.

Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 9.

Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 10.

Typical current consumption on VBAT with RTC on vs. temperature at

different VBAT values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 11.

Typical current consumption in Stop mode with regulator in Run mode

versus temperature at different VDD values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 12.

Typical current consumption in Stop mode with regulator in Low-power

mode versus temperature at different VDD values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 13.

Typical current consumption in Standby mode versus temperature at

different VDD values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 14.

High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 15.

Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 16.

Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 17.

Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 18.

Standard I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 19.

Standard I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 20.

5 V tolerant I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 21.

5 V tolerant I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 22.

I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Figure 23.

Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Figure 24.

I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Figure 25.

SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Figure 26.

SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Figure 27.

SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Figure 28.

I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Figure 29.

I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Figure 30.

USB OTG FS timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . 71

Figure 31.

Ethernet SMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Figure 32.

Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Figure 33.

Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Figure 34.

ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Figure 35.

Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Figure 36.

Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . . 78

Figure 37.

Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . . 78

Figure 38.

12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Figure 39.

LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package

outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Figure 40.

LFBGA100 – 100-ball low profile fine pitch ball grid array, 10 x 10 mm,

0.8 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Figure 41.

LFBGA100 – 100-ball low profile fine pitch ball grid array, 10 x 10 mm,

0.8 mm pitch, package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

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