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STM32F107VB 数据表(PDF) 97 Page - STMicroelectronics |
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STM32F107VB 数据表(HTML) 97 Page - STMicroelectronics |
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97 / 108 page  DocID15274 Rev 10 97/108 STM32F105xx, STM32F107xx Application block diagrams 107 A.2 Ethernet interface solutions Figure 53. MII mode using a 25 MHz crystal 1. HCLK must be greater than 25 MHz. 2. Pulse per second when using IEEE1588 PTP, optional signal. Figure 54. RMII with a 50 MHz oscillator 1. HCLK must be greater than 25 MHz. MCU Ethernet MAC 10/100 Ethernet PHY 10/100 PLL HCLK XT1 PHY_CLK 25 MHz MII_RX_CLK MII_RXD[3:0] MII_RX_DV MII_RX_ER MII_TX_CLK MII_TX_EN MII_TXD[3:0] MII_CRS MII_COL MDIO MDC HCLK(1) PPS_OUT(2) XTAL 25 MHz STM32F107xx OSC TIM2 Timestamp comparator Timer input trigger IEEE1588 PTP MII = 15 pins MII + MDC = 17 pins ai15656 MCU Ethernet MAC 10/100 Ethernet PHY 10/100 PLL HCLK XT1 PHY_CLK 50 MHz RMII_RXD[1:0] RMII_CRX_DV RMII_REF_CLK RMII_TX_EN RMII_TXD[1:0] MDIO MDC HCLK(1) STM32F107xx OSC 50 MHz TIM2 Timestamp comparator Timer input trigger IEEE1588 PTP RMII = 7 pins RMII + MDC = 9 pins ai15657 /2 or /20 synchronous 2.5 or 25 MHz 50 MHz 50 MHz |
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