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STM32F373C8 数据表(PDF) 108 Page - STMicroelectronics

部件名 STM32F373C8
功能描述  ARM® Cortex®-M4 32b MCUFPU, up to 256KB Flash32KB SRAM, timers, 4 ADCs (16-bit Sig. Delta / 12-bit SAR), 3 DACs, 2 comp., 2.0-3.6 V
PDF  137 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STM32F373C8 数据表(HTML) 108 Page - STMicroelectronics

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Electrical characteristics
STM32F373xx
108/137
DocID022691 Rev 7
Figure 31. USB timings: definition of data signal rise and fall time
6.3.24
CAN (controller area network) interface
Refer to Section 6.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics (CAN_TX and CAN_RX).
6.3.25
SDADC characteristics
Table 73. USB: Full-speed electrical characteristics(1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Driver characteristics
tr
Rise time(2)
CL = 50 pF
4
-
20
ns
tf
Fall time(2)
CL = 50 pF
4
-
20
ns
trfm
Rise/ fall time matching
tr/tf
90
-
110
%
VCRS
Output signal crossover voltage
-
1.3
-
2.0
V
Output driver
Impedance(3)
ZDRV
driving high and
low
28
40
44
Ω
1. Guaranteed by design.
2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB Specification - Chapter
7 (version 2.0).
3. No external termination series resistors are required on USB_DP (D+) and USB_DM (D-), the matching impedance is
already included in the embedded driver.
Table 74. SDADC characteristics (1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Note
VDDSDx
Power
supply
Slow mode (fADC = 1.5 MHz)
2.2
-
VDDA
V
-
Normal mode (fADC = 6 MHz)
2.4
-
VDDA
-
fADC
SDADC
clock
frequency
Slow mode (fADC = 1.5 MHz)
0.5
1.5
1.65
MHz
-
Normal mode (fADC = 6 MHz)
0.5
6
6.3
-
VREFSD+
Positive
ref. voltage
-1.1
-
VDDSDx
V-



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