71M6543HT-IGTRSLASHF datasheet(62/75 Pages) MAXIM

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71M6543FT/71M6543HT/

71M6543GT/71M6543GHT

Energy Meter ICs

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Table 13. I/O RAM Locations in Alphabetical Order (continued)

Meter Calibration

Once the 71M654xT energy meter device has been

installed in a meter system, it must be calibrated. A com-

plete calibration includes:

• Establishment of the reference temperature (typically

22°C).

• Calibration of the metrology section: calibration for toler-

ances of the current sensors, voltage dividers and sig-

nal conditioning components as well as of the internal

reference voltage (VREF) at the reference temperature.

The metrology section can be calibrated using the gain

and phase adjustment factors accessible to the CE. The

gain adjustment is used to compensate for tolerances of

components used for signal conditioning, especially the

resistive components. Phase adjustment is provided to

compensate for phase shifts introduced by the current

sensors or by the effects of reactive power supplies.

Due to the flexibility of the MPU firmware, any calibration

method, such as calibration based on energy, or current

and voltage can be implemented. It is also possible to

implement segment-wise calibration (depending on cur-

rent range).

The 71M6543FT/HT/GT/GHT support common industry

standard calibration techniques, such as single-point

(energy-only), multipoint (energy, VRMS, IRMS), and auto-

calibration.

Contact Maxim Integrated to obtain a copy of the latest

calibration spreadsheet file for the 71M654xT.

Firmware Interface

Overview: Functional Order

The I/O RAM locations at addresses 0x2000 to 0x20FF

have sequential addresses to facilitate reading by the

MPU. These I/O RAM locations are usually modified only

atpower-up.Theseaddressesareanalternativesequen-

tial address to subsequent addresses (above 0x2100).

For instance, EQU[2:0] can be accessed at I/O RAM

0x2000[7:5] or at I/O RAM 0x2106[7:5].

Unimplemented (U) and reserved (R) bits are shaded in

light gray. Unimplemented bits are identified with a ‘U’.

Unimplemented bits have no memory storage, writing

them has no effect, and reading them always returns zero.

Reserved bits are identified with an ‘R’, and must always be

written with a zero. Writing values other than zero to reserved

bits may have undesirable side effects and must be avoided.

Nonvolatile bits are shaded in dark gray. Nonvolatile bits

are backed up during power failures if the system includes

a battery connected to the VBAT pin.

I/O RAM Map: Details

Writable bits are written by the MPU into configuration

RAM. Typically, they are initially stored in flash memory

and copied to the configuration RAM by the MPU. Some

ofthemorefrequentlyprogrammedbitsaremappedtothe

MPU SFR memory space. The remaining bits are mapped

to the address space 0x2XXX. The RST and WK columns

describe the bit values upon reset and wake, respectively.

No entry in one of these columns means the bit is either

read-only or is powered by the NV supply and is not initial-

ized. Write-only bits return zero when they are read.

Locations that are shaded in grey are nonvolatile (i.e.,

battery-backed).

NAME

LOCATION RSTWK DIR

DESCRIPTION

WF_DIO55

28B1[0]

– R DIO55wakeflagbit.IfDIO55isconfiguredtowakethepart,thisbitissetwheneverthede-bouncedversionof

DIO55rises.ItisheldinresetifDI055isnotconfiguredforwakeup.

WF_TEMP

28B1[6]

– R Indicates that the temperature range check hardware caused the part to wake up.

WAKE_ARM

28B2[5]

– R/W Arms the WAKE timer and loads it with WAKE_TMR[7:0]. When SLEEP or LCD_ONLY is asserted by the MPU, the

WAKE timer becomes active.

WF_PB

28B1[3]

–

– R Indicates that the PB caused the part to wake.

WF_RX

28B1[4]

– R Indicates that RX caused the part to wake.

WF_CSTART

WF_RST

WF_RSTBIT

WF_OVF

WF_ERST

WF_BADVDD

28B0[7]

28B0[6]

28B0[5]

28B0[4]

28B0[3]

28B0[2]

– R Indicates that the Reset pin, Reset bit, ERST pin, Watchdog timer, the cold start detector, or bad VBAT caused the

part to reset.

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