71M6543HT-IGTRSLASHF datasheet(34/75 Pages) MAXIM

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71M6543FT/71M6543HT/

71M6543GT/71M6543GHT

Energy Meter ICs

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Digital I/O and LCD Segment Drivers

The 71M6543FT/HT/GT/GHT combines most DIO pins

with LCD segment drivers. Each SEG/DIO pin can be

configured as a DIO pin or as a segment (SEG) driver pin.

On reset or power-up, all DIO pins are DIO inputs until

they are configured as desired under MPU control. The

pin function can be configured by the I/O RAM registers

LCD_MAPn. Setting the bit corresponding to the pin

in LCD_MAPn to 1 configures the pin for LCD, setting

LCD_MAPn to 0 configures it for DIO.

Once a pin is configured as DIO, it can be configured

independently as an input or output. The PB pin is a dedi-

cated digital input and is not part of the SEGDIO system.

Some pins (SEGDIO2 through SEGDIO11 and PB) can

be routed to internal logic such as the interrupt control-

ler or a timer channel. This routing is independent of the

direction of the pin, so that outputs can be configured to

cause an interrupt or start a timer.

A total of 32 combined SEG/DIO pins plus 5 SEG outputs

are available for the 71M6543FT/HT/GT/GHT. These pins

can be categorized as follows:

17 combined SEG/DIO segment pins:

• SEGDIO4…SEGDIO5 (2 pins)

• SEGDIO9…SEGDIO14 (6 pins)

• SEGDIO19…SEGDIO25 (7 pins)

• SEGDIO44…SEGDIO45 (2 pins)

15 combined SEG/DIO segment pins shared with other

functions:

• SEGDIO0/WPULSE, SEGDIO1/VPULSE (2 pins)

• SEGDIO2/SDCK, SEGDIO3/SDATA (2 pins)

• SEGDIO6/XPULSE, SEGDIO7/YPULSE (2 pins)

• SEGDIO8/DI (1 pin)

• SEGDIO26/COM5, SEGDIO27/COM4 (2 pins)

• SEGDIO36/SPI_CSZ…SEGDIO39/SPI_CKI (4 pins)

• SEGDIO51/OPT_TX, SEGDIO55/OPT_RX (2 pins)

5 dedicated SEG segment pins are available:

• ICE Inteface pins: SEG48/E_RXTX, SEG49/E_TCLK,

SEG50/E_RST (3 pins)

• Test Port pins: SEG46/TMUX2OUT, SEG47/TMUXOUT

(2 pins)

There are four dedicated common segment outputs

(COM0…COM3) plus the two additional shared common

segment outputs that are listed under combined SEG/DIO

shared pins (SEGDIO26/COM5, SEGDIO27/COM4).

Thus, in a configuration where none of these pins are

used as DIOs, there can be up to 37 LCD segment pins

with 4 commons, or 35 LCD segment pins with 6 com-

mons. And in a configuration where LCD segment pins

are not used, there can be up to 32 DIO pins.

LCD Drivers

The LCD drivers are grouped into up to six commons

(COM0 – COM5) and up to 56 segment drivers. The

LCD interface is flexible and can drive 7-segment digits,

14-segments digits or annunciator symbols.

LCD voltage can be taken from the VLCD pin or the

VV3P3SYS pin. A contrast DAC regulates VLCD from

either VBAT or VV3P3SYS.

The LCD system has the ability to drive up to six seg-

ments per SEG driver. If the display is configured with six

back planes, the 6-way multiplexing minimizes the num-

ber of SEG pins required to drive a display. This maxi-

mizes the number of DIO pins available to the application.

If 5-state multiplexing is selected, SEGDIO27 is converted

to COM4. If 6-state multiplexing is selected, SEGDIO26 is

converted to COM5.

The LCD_ON and LCD_BLANK bits are an easy way to

either blank the LCD display or to turn all segments on.

Neither bit affects the contents of the LCD data stored in

the LCDSEG_DIO[ ] registers. In comparison, LCD_RST

(I/O RAM 0x240C[2]) clears all LCD data to zero. LCD_

RST affects only pins that are configured as LCD.

The LCD can be driven in static, ½ bias, and ⅓ bias

modes. Note that COM pins that are not required in a

specific mode maintain a ‘segment off’ state rather than

GND, VCC, or high impedance.

The segment drivers SEGDIO22 and SEGDIO23 can be

configured to blink at either 0.5 Hz or 1 Hz. The blink rate

is controlled by LCD_Y. There can be up to six segments

connected to each of these driver pins. The I/O RAM fields

LCD_BLKMAP22[5:0] and LCD_BLKMAP23[5:0] identify

which pixels, if any, are to blink. LCD_BLKMAP22[5:0]

and LCD_BLKMAP23[5:0] are nonvolatile.

The LCD bias may be compensated for temperature

using the LCD_DAC[4:0] field. The bias may be adjusted

from 1.4 V below the 3.3 V supply (VV3P3SYS in MSN

mode and VBAT in BRN and LCD modes). When the

LCD_DAC[4:0] field is set to 000, the DAC is bypassed

and powered down. This can be used to reduce current

in LCD mode.

The 71M6543FT/HT/GT/GHT has 56 LCD driver pins

available, and can drive up to 336 segments.

71M6543HT-IGTR/F 数据表(PDF) 34 Page - Maxim Integrated Products

71M6543HT-IGTR/F 数据表(HTML) 34 Page - Maxim Integrated Products

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