ADP1031ACPZ-2-R7 datasheet(30/38 Pages) AD

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ADP1031

Data Sheet

Rev. A | Page 30 of 38

FLYBACK REGULATOR COMPONENTS SELECTION

Input Capacitor

An input capacitor must be placed between the VINP pin and

ground. Ceramic capacitors greater than or equal to 3.3 µF over

temperature and voltage are recommended. The input capacitor

reduces the input voltage ripple caused by the switching current.

Place the input capacitor as close as possible to the VINP and

PGNDP pins to reduce input voltage spikes. The voltage rating of

the input capacitor must be greater than the maximum input

voltage.

Output Capacitor

Higher output capacitor values reduce the output voltage ripple

and improve load transient response. When choosing this value,

it is also important to account for the loss of capacitance due to

the output voltage dc bias. A 4.7 µF capacitor is recommended

as a balance between performance and size.

Ripple Current vs. Capacitor Value

The output capacitor value must be chosen to minimize the

output voltage ripple while considering the increase in size and

cost of a larger capacitor. Use the following equation to calculate

the output capacitance:

COUT = (LPRI × ISWP2)/(2 × VOUT1 × ΔVOUT1)

where:

COUT is the capacitance of the flyback output capacitor.

LPRI is the primary inductance of the transformer.

ISWP is the peak switch current.

VOUT1 is the flyback regulator output voltage.

ΔVOUT1 is the allowable flyback regulator output ripple.

Schottky Diode

A Schottky diode with low junction capacitance is recommended

for D1. At higher output voltages and especially at higher

switching frequencies, the junction capacitance is a significant

contributor to efficiency. Choose an output diode with a

forward current rating (IF) that is greater than the maximum

load requirement and with a reverse voltage rating (VR) that is

greater than the summation of the maximum supply voltage

(VINP (MAX)) and the maximum output voltage (VOUT1 (MAX)).

Transformer

The transformer used with the ADP1031 is an important

component within the system, in terms of efficiency and maximum

output power capability. Analog Devices worked with a number of

leading magnetic component suppliers to develop a number of

transformer designs for use with the ADP1031. These designs are

listed in Table 16. A number of factors must be taken into account

when designing a transformer for use with the ADP1031.

Turn Ratio

The ADP1031 requires the use of a transformer with a primary

to secondary turn ratio of 1:1 to start up properly.

Primary Inductance

The ADP1031 operates with a transformer with an inductance

in the 80 µH to 560 µH range. However, it is recommended to

choose an inductance value that results in the flyback output voltage

(VOUT1) divided by the transformer primary inductance being

less than or equal to 140,000 to maintain control loop stability.

VOUT1/LPRI ≤ 140,000

where:

VOUT1 is the flyback regulator output voltage.

LPRI is the primary side inductance of the transformer.

Using a transformer at the lower end of the inductance range may

result in a smaller transformer but also reduces the output power

capabilities due to larger ac ripple current through the transformer.

Conversely, operating at higher inductance can result in higher

output power at the expense of a potentially larger transformer.

Flyback Transformer Saturation Current

Do not exceed the saturation current of the transformer in

operation or this may lead to much higher losses and overall

lower system efficiency. Choose a transformer with a saturation

current rating that is greater than the expected peak switch

current (ISWP) across line and load conditions.

Series Winding Resistance

In power loss sensitive applications, keep the series resistance

of the primary and secondary windings as low as possible to

improve overall efficiency.

Leakage Inductance and Clamping Circuits

When choosing a transformer to operate with the ADP1031,

minimize transformer leakage inductance. Leakage inductance

causes a voltage spike to appear on the SWP node when the

flyback regulator switch is off due to energy storage in the

leakage inductance that is not transferred to the output. The

voltage spike is more prominent at higher load currents and

increases with higher leakage inductance. It is important to

keep the voltage spikes lower than the voltage rating of the

flyback switch that drives the SWP pin. Margin must be built

in to any design to avoid exceeding this limit if no clamp or

snubber circuit is used to protect the flyback switch.

To estimate the leading voltage spike at the SWP pin when the

switch turns off, use the following equation:

VPEAK = IPEAK × (LLEAK/(CP + CSWP))1/2 + VINP + VOUT1 + VD

where:

VPEAK is the voltage spike amplitude.

IPEAK is the peak current on the flyback switch.

LLEAK is the leakage inductance of the transformer.

CP is the parasitic capacitance of the transformer.

CSWP is the capacitance on the flyback switch.

VINP is the input supply voltage.

VOUT1 is the output voltage of the flyback regulator.

VD is the forward voltage drop across the rectifier diode.

A snubber or clamp circuit can protect the flyback switch for

cases where the leakage inductance is too high for application

conditions. Two common types of clamping circuit are the

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