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ADP1031ACPZ-2-R7 数据表(PDF) 6 Page - Analog Devices |
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ADP1031ACPZ-2-R7 数据表(HTML) 6 Page - Analog Devices |
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6 / 38 page  ADP1031 Data Sheet Rev. A | Page 6 of 38 Parameter Symbol Min Typ Max Unit Test Conditions/Comments Current-Limit Threshold ILIM (INVERTER) 280 300 320 mA SW3 Leakage Current PMOS 0.03 0.5 µA VSW3 = −24 V NMOS 0.03 0.5 µA VSW3 = 24 V Switching Frequency fSW (INVERTER) 117.5 125 132.5 kHz SYNC = low or high fSYNC/4 kHz SYNC = external clock Minimum On Time 178 ns Soft Start Timer tSS (INVERTER) 8 ms Active Pull-Down Resistor RPD (INVERTER) 350 Ω 1.23 V < VOUT1 < 4.5 V ISOLATORS, DC SPECIFICATIONS MCK, MSS, MO, SO, MGPI1, MGPI2, SGPI3 Input Threshold Logic High VIH 0.7 × VxVDD V VxVDD = VMVDD or VSVDDx Logic Low VIL 0.3 × VxVDD V VxVDD = VMVDD or VSVDDx Input Current II −1 +1 µA 0 V ≤ VINPUT ≤ VxVDD SCK, SSS, SI, MI Output Voltage Logic High VOH VxVDD − 0.1 V IOx2 = −20 µA, VIx = VIxH3 VxVDD − 0.4 V IOx2 = −2 mA, VIx = VIxH3 Logic Low VOL 0.1 V IOx2 = 20 µA, VIx = VIxL4 0.15 0.4 V IOx2 = 2 mA, VIx = VIxL4 SGPO1, SGPO2, MGPO3 Output Voltage Logic High VOH VxVDD − 0.1 V IOx2 = −20 µA, VIx = VIxH3 VxVDD − 0.4 V IOx2 = −500 µA, VIx = VIxH3 Logic Low VOL 0.1 V IOx2 = 20 µA, VIx = VIxL4 0.15 0.4 V IOx2 = 500 µA, VIx = VIxL4 SCK, SI, MI Tristate Leakage −1 0.01 1 µA MSS = logic high −1 0.01 1 µA VOx5 = VxVDD ISOLATORS, SWITCHING SPECIFICATION MCK, MSS, MO, SO SPI Clock Rate SPIMCK 16.6 MHz Latency 100 125 ns Delay from MSS going low to the first data out is valid Input Pulse Width tPW 17 ns Within PWD limit Input Pulse Width Distortion tPWD 0.25 6.5 ns |tPLH − tPHL| Channel Matching Codirectional tPSKCD 0.5 5.5 ns Opposing Direction tPSKOD 0.5 4 ns |
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