ADP1031

Data Sheet

Rev. A | Page 10 of 38

ABSOLUTE MAXIMUM RATINGS

Table 6.

Parameter

Rating

VINP to PGNDP

61 V

SWP to VINP

VINP + 70 V or 110 V,

whichever is lower

SLEW to GNDP

−0.3 V to VINP + 0.3 V

EN to GNDP

−0.3 V to +61 V

VOUT1 to SGND2

35 V

FB1 to SGND2

−0.3 V to VOUT1 + 0.3 V

VOUT1 to VOUT3

61 V

SW2 to SGND2

−0.3 V to VOUT1 + 0.3 V

VOUT2 to SGND2

6 V

SW3 to SGND2

VOUT3 − 0.3 V to

VOUT1 + 0.3 V

VOUT3 to SGND2

−26 V to +0.3 V

FB3 to VOUT3

+3.3 V to −0.3 V

SVDD1 to SGND1

6.0 V

SVDD2 to SGND2

6.0 V

SSS, SCK, SI, SO to SGND1

−0.3 V to SVDD1 + 0.3 V

SGPO1, SGPO2, SGPI3 to SGND2

−0.3 V to SVDD2 + 0.3 V

SYNC to SGND2

−0.3 V to +6 V

MVDD to MGND

6.0 V

MSS, MCK, MO, MI to MGND

−0.3 V to MVDD + 0.3 V

MGPI1, MGPI2, MGPO3 to MGND

−0.3 V to MVDD + 0.3 V

PWRGD to MGND

−0.3 V to MVDD + 0.3 V

Common-Mode Transients

±100 kV/µs

Operating Junction Temperature

−40°C to +125°C

Storage Temperature Range

−65°C to +150°C

Lead Temperature

JEDEC industry standard

Soldering Conditions

JEDEC J-STD-020

1

Power dissipated on chip must be derated to keep the junction temperature

below 125°C.

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

THERMAL RESISTANCE

Thermal performance is directly linked to printed circuit board

(PCB) design and operating environment. Close attention to

PCB thermal design is required.

is measured at the top of the package and is independent of the

case temperature in the application.

Table 7. Thermal Resistance

Unit

CP-41-1

50.4

33.1

25

°C/W

1

9 mm × 7 mm LFCSP with omitted pins for isolation purposes.

2

Thermal impedance simulated values are based on a JEDEC 2S2P thermal

test board with 19 thermal vias. See JEDEC JESD-51.

3

Case temperature was measured at the center of the package.

4

Board temperature was measured near Pin 1.

ESD CAUTION

Parameter

Value

Constraint

60 Hz AC Voltage

300 V rms

20-year lifetime at 0.1% failure rate, zero average voltage

DC Voltage

1

See the Insulation Lifetime section for more details.

2

Other pollution degree and material group requirements yield a different limit.

3

Some system level standards allow components to use the printed wiring board (PWB) creepage values. The supported dc voltage may be higher for those standards.