ADP5034ACPZ-R7 datasheet(1/28 Pages) AD

部件名	ADP5034ACPZ-R7

功能描述	Dual 3 MHz, 1200 mA Buck Regulators with Two 300 mA LDOs

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制造商	AD [Analog Devices]

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Dual 3 MHz, 1200 mA Buck

Regulators with Two 300 mA LDOs

Data Sheet

ADP5034

Rev. E

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FEATURES

Main input voltage range: 2.3 V to 5.5 V

Two 1200 mA buck regulators and two 300 mA LDOs

24-lead, 4 mm × 4 mm LFCSP or 28-lead TSSOP package

Regulator accuracy: ±1.8%

Factory programmable or external adjustable VOUTx

3 MHz buck operation with forced PWM and auto PWM/PSM

modes

BUCK1/BUCK2: output voltage range from 0.8 V to 3.8 V

LDO1/LDO2: output voltage range from 0.8 V to 5.2 V

LDO1/LDO2: input supply voltage from 1.7 V to 5.5 V

LDO1/LDO2: high PSRR and low output noise

APPLICATIONS

Power for processors, ASICS, FPGAs, and RF chipsets

Portable instrumentation and medical devices

Space constrained devices

GENERAL DESCRIPTION

The ADP5034 combines two high performance buck regulators

and two low dropout (LDO) regulators. It is available in either a

24-lead 4 mm × 4 mm LFCSP or a 28-lead TSSOP package.

The high switching frequency of the buck regulators enables tiny

multilayer external components and minimizes the board space.

When the MODE pin is set to high, the buck regulators operate in

forced PWM mode. When the MODE pin is set to low, the buck

regulators operate in PWM mode when the load is above a pre-

defined threshold. When the load current falls below a predefined

threshold, the regulator operates in power save mode (PSM),

improving the light load efficiency.

Table 1. Family Models

Model

Channels

Maximum

Current

Package

ADP5023

2 Buck,1 LDO

800 mA,

300 mA

LFCSP (CP-24-10)

ADP5024

2 Buck,1 LDO

1.2 A,

300 mA

LFCSP (CP-24-10)

ADP5034

2 Buck,2 LDOs

1.2 A,

300 mA

LFCSP (CP-24-10),

TSSOP (RE-28-1)

ADP5037

2 Buck,2 LDOs

800 mA,

300 mA

LFCSP (CP-24-10)

ADP5033

2 Buck,2 LDOs with

2 EN pins

800 mA,

300 mA

WLCSP (CB-16-8)

The two bucks operate out of phase to reduce the input capaci-

tor requirement. The low quiescent current, low dropout voltage,

and wide input voltage range of the ADP5034 LDOs extend the

battery life of portable devices. The ADP5034 LDOs maintain

power supply rejection greater than 60 dB for frequencies as

high as 10 kHz while operating with a low headroom voltage.

Regulators in the ADP5034 are activated through dedicated

enable pins. The default output voltages can be externally set in

the adjustable version, or factory programmable to a wide range

of preset values in the fixed voltage version.

TYPICAL APPLICATION CIRCUIT

VIN1

VIN3

EN1

PWM

PSM/PWM

2.3V TO

5.5V

SW1

FB1

R2

R1

VOUT1

PGND1

MODE

C5

10µF

VOUT1 AT

1200mA

VOUT2 AT

1200mA

VOUT3 AT

300mA

VOUT4 AT

300mA

L1 1µH

EN1

BUCK1

MODE

C3

1µF

C2

4.7µF

C1

4.7µF

AVIN

CAVIN

0.1µF

C4

1µF

VIN2

EN2

AGND

EN2

BUCK2

MODE

EN3

1.7V TO

5.5V

EN4

VIN4

ON

OFF

ON

OFF

EN3

LDO1

(ANALOG)

ADP5034

HOUSEKEEPING

SW2

FB2

R4

R3

VOUT2

PGND2

C6

10µF

L2 1µH

FB3

R6

R5

VOUT3

C7

1µF

FB4

R8

R7

VOUT4

C8

1µF

EN4

LDO2

(DIGITAL)

Figure 1.

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