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ADP5034ACPZ-R7 数据表(PDF) 16 Page - Analog Devices |
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ADP5034ACPZ-R7 数据表(HTML) 16 Page - Analog Devices |
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16 / 28 page  ADP5034 Data Sheet Rev. E | Page 16 of 28 THEORY OF OPERATION LDO CONTROL LDO UNDERVOLTAGE LOCKOUT SOFT START PWM/ PSM CONTROL BUCK2 DRIVER AND ANTISHOOT THROUGH SOFT START DRIVER AND ANTISHOOT THROUGH OSCILLATOR THERMAL SHUTDOWN SYSTEM UNDERVOLTAGE LOCKOUT PWM COMP GM ERROR AMP GM ERROR AMP PSM COMP PSM COMP LOW CURRENT ILIMIT PWM COMP LOW CURRENT ILIMIT R1 R2 ADP5034 VOUT1 VOUT2 VIN1 AVIN SW1 PGND1 VIN3 AGND VOUT3 FB3 PGND2 SW2 VIN2 AVIN 75Ω ENBK1 ENABLE AND MODE CONTROL EN1 ENBK1 ENBK2 ENLDO1 ENLDO2 600Ω ENLDO2 75Ω ENBK2 EN2 EN3 EN4 600Ω ENLDO1 LDO CONTROL LDO UNDERVOLTAGE LOCKOUT R3 R4 VIN4 VOUT4 AVIN FB4 B SEL OP MODE MODE2 A Y MODE FB1 FB2 PWM/ PSM CONTROL BUCK1 Figure 46. Functional Block Diagram POWER MANAGEMENT UNIT The ADP5034 is a micropower management unit (micro PMU) combining two step-down (buck) dc-to-dc converters and two low dropout linear regulators (LDOs). The high switching frequency and tiny 24-lead LFCSP package allow for a small power management solution. To combine these high performance regulators into the micro PMU, there is a system controller allowing them to operate together. The buck regulators can operate in forced PWM mode if the MODE pin is at a logic high level. In forced PWM mode, the buck switching frequency is always constant and does not change with the load current. If the MODE pin is at logic low level, the switching regulators operate in auto PWM/PSM mode. In this mode, the regulators operate at fixed PWM frequency when the load current is above the PSM current threshold. When the load current falls below the PSM current threshold, the regulator in question enters PSM, where the switching occurs in bursts. The burst repetition rate is a function of the current load and the output capacitor value. This operating mode reduces the switching and quiescent current losses. The auto PWM/PSM mode transition is controlled independently for each buck regulator. The two bucks operate synchronized to each other. The ADP5034 has individual enable pins (EN1 to EN4) control- ling the activation of each regulator. The regulators are activated by a logic level high applied to the respective EN pin. EN1 controls BUCK1, EN2 controls BUCK2, EN3 controls LDO1, and EN4 controls LDO2. Regulator output voltages are set through external resistor dividers or can be optionally factory programmed to default values (see the Ordering Guide section). When a regulator is turned on, the output voltage ramp rate is controlled through a soft start circuit to avoid a large inrush current due to the charging of the output capacitors. |
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