ADP2450ASTZ-5-R7 datasheet(33/40 Pages) AD

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Data Sheet

ADP2450

Rev. B | Page 33 of 40

CIRCUIT BOARD LAYOUT RECOMMENDATIONS

In any switching power supply, there are some circuit paths that

carry high dI/dt, the current changing rate, which creates spikes

and noises. Some circuit paths are sensitive to noise, such as

feedback traces, error amplifier input and output traces, which

must be devoid of spikes and noises. The key to proper PCB

layout is to identify these critical paths and arrange the

components and the copper area accordingly to keep the paths

away from noise sources. When designing PCB layouts, be sure

to keep high current loops small. In addition, keep sensitive

trances and components away from the switching nodes and

their associated components.

The following sections describe the recommended layout rules

for the ADP2450. Figure 73 shows a recommended PCB layout

for single coil application.

GROUND PLANES

Use separate analog ground planes and power ground planes.

Connect the ground reference of sensitive analog circuitry, such

as output voltage divider components, amplifier output resistor

and capacitor (RC) filters, and a common voltage reference, to

analog ground. Connect the ground reference of the power

components, such as input and output capacitors, and external

MOSFETs to power ground. Use internal ground planes to connect

the analog ground plane and the power ground plane together.

In addition, connect the exposed pad of the ADP2450 to a large,

external copper ground plane to maximize the power

dissipation capability and minimize junction temperature.

SWITCH NODE

The switch node is the noisiest location in the switch power

supply circuit with large ac and dc voltages and currents. The

following two switch nodes are in the ADP2450 circuit: the

external MOSFET drain of the boost shunt controller and the

SW pin of the buck regulator. These nodes must be wide to

prevent the resistive voltage from dropping. To minimize the

generation of capacitively coupled noise, the total area of each

switch node must be small.

For the boost shunt controller, place the bridge rectifiers, the

MOSFET, the rectifier diode, and the output capacitors as close

as possible to each other, and use wide short traces or copper

planes. Ensure that the high current loop traces are as short and

as wide as possible.

For the buck regulator, place the input capacitor, the inductor,

and the output capacitor as close as possible to the IC, and use

short traces. Make the high current path from the input

capacitor through the inductor, the output capacitor, and the

power ground plane back to the input capacitor as short as

possible. In addition, ensure that the high current path from the

power ground plane through the inductor and output capacitor

back to the power ground plane is as short as possible by tying

the ADP2450 PGND2 pin to the power ground plane as close as

possible to the input and output capacitors.

FEEDBACK PATHS

The feedback traces of FB1 and FB2 are very sensitive to noise.

Place the feedback resistor divider networks as close as possible

to the FBx pins to prevent noise pickup. Minimize the length of

the feedback traces that connect the top of the feedback resistor

dividers to the output while keeping these traces away from the

high current traces and the switching nodes to avoid noise

pickup. To further reduce noise pickup, place an analog ground

plane on either side of the FBx traces and ensure that the traces

are as short as possible to reduce the parasitic capacitance pickup.

POWER TRACES

In the ADP2450 circuit design, the output of the boost shunt

controller, VOUT1, is connected to the input of buck regulator.

The output of buck regulator, VOUT2, is connected to the AVDD

providing power to the internal PGAs. These two traces are

power traces and may carry high currents. Use internal power

planes for the power trace connections and keep these power

traces as short and wide as possible to minimize the voltage

drops on them under high current situations.

SIGNAL PATHS

The input and output of all the amplifiers, the common voltage

input, the TRG trace, and the VTRP signals are all signal paths.

Keep these signal paths away from switch nodes and high

current paths to avoid noise pickup. Connect the ground

reference of these signal paths to the analog ground plane using

short and wide traces.

GATE DRIVER PATHS

The gate drive traces, DRV and GATE, of external MOSFETs

handle high dI/dt and tend to produce noise and ringing. The

gate drive traces must be as short and direct as possible. Avoid

using feedthrough vias in the gate drive traces. If vias are

needed, it is recommended to use two relatively large ones in

parallel to reduce the peak current density and the current in

each via. If the overall PCB layout is less than optimal, slowing

down the gate drive slightly can help reduce noise and ringing.

It may be helpful to place small value resistors, between 2 Ω and

10 Ω, on the DRV and GATE pins. These locations can be

populated with 0 Ω resistors if resistance is not needed. Note

that the added gate resistance increases the switching rise and

fall times, as well as switching power loss in the MOSFETs.

ADP2450ASTZ-5-R7 数据表(PDF) 33 Page - Analog Devices

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