ADP2450ASTZ-5-R7 datasheet(23/40 Pages) AD

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Data Sheet

ADP2450

Rev. B | Page 23 of 40

BUCK REGULATOR

The buck regulator in the ADP2450 uses a current mode

control scheme for stability and transient response.

The buck regulator operates in a 1.2 MHz fixed switching

frequency. The regulator integrates the soft start and

compensation circuit to reduce the external components and

provide an easy to use solution. The soft-start time is 400 μs for

the fixed output version and is 1.6 ms for the adjustable output

version.

The ADP2450 uses the emulated current ramp voltage for cycle

by cycle current-limit protection to prevent current runaway.

When the emulated current ramp voltage reaches the current-

limit threshold, the high-side MOSFET turns off and the low-

side MOSFET turns on until the next cycle. The overcurrent

counter increments during this cycling process. If the overcurrent

does not occur in the next cycle, the overcurrent counter decreases.

If the overcurrent counter reaches 10 or the voltage on the

FB2 pin drops below 0.2 V after soft start, the buck regulator

enters into hiccup mode. During hiccup mode, both the high-

side MOSFET and low-side MOSFET are turned off. The buck

regulator remains in hiccup mode for 1024 clock cycles and

then attempts to restart with a soft start. If the current-limit

fault is cleared, the buck regulator resumes normal operation.

Otherwise, the buck regulator reenters hiccup mode.

The low-side MOSFET in the buck regulator also sinks current

from the load. If the low-side sink current exceeds the sink

current-limit threshold, both the low-side and high-side

MOSFETs are turned off until the next cycle starts.

The buck regulator only works when the voltage on the VPTH pin

is higher than the VPTH rising threshold.

BOOTSTRAP CIRCUIT

The ADP2450 includes a regulator to provide the gate driver

voltage for the high-side N-MOSFET of the buck regulator. It

uses differential sensing method to generate a 5 V bootstrap

voltage between the BST and the SW pins.

It is recommended to place a 0.1 μF, X7R or X5R ceramic

capacitor between the BST and the SW pins.

POWER MONITOR AND RESET

The output voltage of the buck regulator is monitored through

the FB2 pin. When the voltage on FB2 pin is below the reset

threshold, the RSTO pin is pulled down. When the voltage on

FB2 pin is above the reset threshold, the RSTO pin is released

and can be pulled up by an external voltage source. A delay time

is designed for the RSTO pin to ensure that no glitch occurs on

the RSTO pin. There are four following options for the rising

delay time: 0.5 ms, 1 ms, 2 ms, and 5 ms. The falling delay time is

fixed at 10 μs.

PROGRAMMABLE GAIN AMPLIFIER

The ADP2450 integrates four low offset, low power programmable

gain amplifiers (PGA1, PGA2, PGA3, and PGA4). The gain of

these amplifiers is programmable through the GAIN0 and

GAIN1 pins.

Connect a resistor between the GAIN1 pin and ground to set

different gains.

Pull up the GAIN0 pin to high or pull down the GAIN0 pin to

low to choose different gain ranges.

A total of 15 gains can be obtained via different combinations

of GAIN0 and GAIN1 settings. Table 8 shows the relationship

between the gain and the GAIN0 and GAIN1 configurations.

Table 8. Gain Setting for PGAx

Resistance on GAIN1 (kΩ )

GAIN

GAIN0 = Low

GAIN0 = High

0.75

42.2

63.4

1.25

95.3

1.5

143

1.75

215

324

2.5

AVDD

The AVDD pin provides the voltage supply for the programmable

gain amplifiers, and the output voltage of the amplifiers are

clamped between zero and VAVDD.

The output voltage of PGAx is calculated with the following

equation:

VCOM

EOUTx

EINx

GAIN





where:

VEOUTx is the voltage on the EOUTx pin.

VVCOM is the voltage on VCOM pin.

VEINx is the voltage on the EINx pin.

GAIN is the gain value programmed by the GAIN0 and

GAIN1 pins according to Table 8.

In a Rogowski application, as shown in Figure 75, connect a

resistor between RCOM and ground to compensate for the

passive, integrated dc resistor. Connect VCOM to AVDD or to a

reference voltage derived from AVDD for the proper start-up

sequence.

In the CT current sense application, connect both the VCOM

and RCOM pins to ground.

ADP2450ASTZ-5-R7 数据表(PDF) 23 Page - Analog Devices

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