SP9502DS/02

SP9502 Dual, 12-Bit, Voltage Output D/A Converter

© Copyright 1999 Sipex Corporation

7

Figure 2. Transfer Function

ZEROING DAC OUTPUTS

While keeping XFER pin high, the DAC outputs can

be set to zero volts two different ways. The first

involvestheCLRandWR2pins. Innormaloperation,

the CLR pin is tied high, thus, disabling the clear

function. By cycling WR2 and CLR through "1"—

"0"—"1" sequence, a digital code of 1000 0000 0000

iswrittentobothDACregisters,producingahalfscale

output or zero volts. The second utilizes the built in

power-on-reset. Usingthisfeature,theSP9502canbe

configured such that during power-up, the second

register will be digitally “zeroed”, producing a zero

volt output at both DAC outputs. This is achieved by

poweringtheunitupwithXFERinahighstate. Thus,

with no external circuitry, the SP9502 can be

powered up with the analog outputs at a known,

zero volt output level.

TEMPORARILY FORCING

BOTH DAC OUTPUTS TO OV

Set WR1=1, CS=1, WR2=0, XFER=0. The DAC

registers can be temporarily forced to 1000 0000

0000 by bringing the CLR pin low. This will

cause the DAC outputs to 0V, while the CLR pin

remains low. When the CLR pin is brought back

high, the digital code at the DAC registers will

again appear at the DAC's digital inputs, and the

analog outputs will return to their previous

values.

–

+

D

D

2048

(

)

D

4,096

A

CS

WR1

B1/B2

WR2

XFER

CLR

FUNCTION

0

1

1

X

X

Address DAC 1 and load input register

0

0

1

X

X

Address DAC 1 and load 4 LSBs

1

1

1

X

X

Address DAC 2 and load input register

1

0

1

X

X

Address DAC 2 and load 4 LSBs

X

**

**

X

1

Transfer data from input registers to DAC registers

X

X

X

X

1

Sets all DAC output voltages to 0V

X

1

1

X

0

0

Temporarily force both DAC output voltages to

0V, while CLR is low

X

1

XXXXX

Invalid state with any other control line active

X

X

1

XXXX

Invalid state with any other control line active

X = Don’t care; ** = Don’t care; however, CS and WR1 = 1 will inhibit changes to the input registers.

Table 2. Control Logic Truth Table