SP9502DS/02

SP9502 Dual, 12-Bit, Voltage Output D/A Converter

© Copyright 1999 Sipex Corporation

4

are forced to 1000 0000 0000 and the DAC outputs

will settle to OV. Active low.

Pin 13 — WR1 — Write Input1 — In conjunction

with CS (pin 14), enables input register selection,

and controls the transfer of data from the input bus

to the input registers. Active low.

Pin 14 — CS — Chip Select — Enables writing

data to input registers and/or transferring data from

input bus to DAC registers.

Pin 15 — V

Pin 16 — DB

Pin 17 — DB

Pin 18 — DB

Pin 19 — DB

Pin 20 — DB

Pin 21 — DB

Pin 22 — DB

Pin 23 — DB

Pin 24 — DB

Pin 25 — DB

Pin 26 — DB

Pin 27 — DB

Pin 28 — N.C. — No Connection.

PINOUT — 28–PIN SOIC & DIP

PIN ASSIGNMENTS

Pin 1 — N.C. — No Connection.

Pin 2 — V

Pin 3 — V

Pin 4 — V

Pin 5 — CLR — Clear. Gated with WR2 (pin 12).

Active low. Clears both DAC outputs to 0V.

Pin 6 — REF IN2 — Reference Input for DAC2.

Pin 7 — GND — Ground.

Pin 8 — B1/B2 — Byte 1/Byte 2 — Selects Data

Input Format. A logic “1” on pin 8 selects the 12–

bit mode, and all 12 data bits are presented to the

DAC(s) unchanged; a logic “0” selects the 8–bit

mode, and the four LSBs are connected to the four

MSBs, allowing an 8–bit MSB–justified interface.

Pin 9 — A — Address for DAC Selection — A

logic “0” selects DAC 1; a logic “1” selects

DAC 2.

Pin 10 — REF IN1 — Reference Input for DAC1.

Pin 11 — XFER — Transfer. Gated with WR2

(pin 12); loads all DAC registers simultaneously.

Active low.

Pin 12 — WR2 — Write Input 2 — In conjunction

with XFER (pin 11), controls the transfer of data

from the input registers to the DAC registers. In

conjunction with CLR (pin 5), the DAC registers

N.C.

CLR

Ref In 2

GND

B1/B2

A

Ref In 1

XFER

WR2

WR1

CS

N.C.

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

SP9502