SP9502DS/02

SP9502 Dual, 12-Bit, Voltage Output D/A Converter

© Copyright 1999 Sipex Corporation

8

H

L

H

L

H

L

CLR

XFER

WR2

140ns, t

H

L

H

L

H

L

WR2

CS

WR1

140ns, t

Data Transfer from

Input Register to DAC's

Loads Input Data to

First Set of Latches

WR

XFER

Figure 4. Timing

Figure 3. Latch Control Options — (Top) Semi–Transparent Latch Mode; (Bottom) Fully–Transparent Latch Mode

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

N.C.

CLR

GND

B1/B2

A

XFER

WR2

WR1

CS

N.C.

SP9502

+5V –5V

12–Bit

Data

Bus

+3V

References GND

Address

Decode &

Control

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

N.C.

CLR

GND

B1/B2

A

XFER

WR2

WR1

CS

N.C.

SP9502

+5V –5V

12–Bit

Data

Bus

+3V

References GND

Address

Decode &

Control

DAC Strobe