Data Sheet

ADIN2299

SPECIFICATIONS

analog.com

Rev. 0 | 5 of 21

Table 2.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

Cycle Time

1

ms

8 bytes of cyclic input and output data, Ethernet

applications processor interface

TIMING CHARACTERISTICS

10 Mbps and 100 Mbps Ethernet MAC Interface Timing

Table 3 through Table 5 and Figure 2 through Figure 4 describe the Ethernet MAC applications processor, interface controller, timing

externally generated Ethernet MAC clock timing and the internal system clock timing, use the following equations:

Table 3. 10 Mbps and 100 Mbps Ethernet MAC Reduced Media Independent Interface (RMII) Receive Signal Timing

Parameter

Min

Max

Unit

ETH0_REFCLK Frequency

50

MHz

ETH0_REFCLK Period1

ns

ETH0_REFCLK Width1

ns

Receive Input Valid to RMII ETH0_REFCLK Rising Edge (Data In Setup)

4

ns

RMII ETH0_REFCLK Rising Edge to Receive Input Invalid (Data In Hold)

2.0

ns

Figure 2. RMII Receive Timing

Table 4. 10 Mbps and 100 Mbps Ethernet MAC RMII Transmit Signal Timing

Parameter

Min

Max

Unit

RMII ETH0_REFCLK Rising Edge to Transmit Output Valid (Data Out Valid)

14

ns

RMII ETH0_REFCLK Rising Edge to Transmit Output Valid (Data Out Hold)

2

ns

Figure 3. RMII Transmit Timing