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PL133-47SC-R 数据表(PDF) 6 Page - Microchip Technology |
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PL133-47SC-R 数据表(HTML) 6 Page - Microchip Technology |
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6 / 20 page ![]() PL133-47 DS20006670A-page 6 2022 Microchip Technology Inc. and its subsidiaries 3.0 NOMINAL PERFORMANCE CHARACTERISTICS U FIGURE 3-1: PL133-47 Additive Phase Jitter: VDD = 3.3V, CLK-100 MHz, Integration Range 2 kHz - 20 MHz, 0.059 ps Typical. When a buffer is used to pass a signal then the buffer will add a little bit of its own noise. The phase noise on the output of the buffer will be a little bit more than the phase noise in the input signal. The noise added by the buffer to the input signal is quantified by the additive phase jitter defined by the following formula: EQUATION 3-1: Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. -160 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 10 100 1000 10000 100000 1000000 10000000 100000000 Offset Frequency (Hz) REF Input PL133-47 Output AdditivePhaseJitter OutputPhaseJitter 2 InputPhaseJitter 2 – = |
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