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ADCA5191ACPZ-R7 数据表(PDF) 7 Page - Analog Devices

部件名 ADCA5191ACPZ-R7
功能描述  5 MHz to 1800 MHz Broadband CATV Amplifier
PDF  24 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADCA5191ACPZ-R7 数据表(HTML) 7 Page - Analog Devices

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Data Sheet
ADCA5191
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
analog.com
Rev. 0 | 7 of 24
Figure 2. Pin Configuration
Table 9. Pin Function Descriptions
Pin No.
Mnemonic
Description
1, 4, 5, 8, 9, 10, 12, 13, 15,
16, 17, 21, 24, 25, 26, 28, 29,
31, 32
NC
No Connect. Do not connect to these pins. Leave these pins floating.
2, 3
RFIP
Positive RF Amplifier Input. RFIP and RFIN form a differential input.
6, 7
RFIN
Negative RF Amplifier Input. RFIP and RFIN form a differential input.
11
BIASA
BIASA (together with BIASB) supplies a portion (~10%) of the IDD and controls the overall bias current of the amplifier.
Configure the BIASA and BIASB pins as shown in Figure 41 with the bias resistor (RBIAS) controlling IDD as illustrated in
Figure 42. Keep the network of passive components between BIASA and VDD close to the device package to minimize
parasitics.
14
BIAS2A
BIAS2A (together with BIAS2B) provides additional RF tuning or bias adjustment for special applications. However, BIAS2A
and BIAS2B are normally left floating.
18, 19
RFON
Negative Amplifier RF Output. A choke inductor is required to provide dc current and RF isolation. A dc blocking capacitor is
also required.
20
RSET
Bias Resistor. Place a 1% resistor between RSET and ground.
22 ,23
RFOP
Positive Amplifier RF Output. A choke inductor is required to provide dc current and RF isolation. A dc blocking capacitor is
also required. See Figure 39, and Figure 40 for specific recommendations.
27
BIAS2B
BIAS2B (together with BIAS2A) provides additional RF tuning or bias adjustment for special applications. However, BIAS2B
and BIAS2A are normally left floating.
30
BIASB
BIASB (together with BIASA) supplies a portion (~10%) of the IDD and controls the overall bias current of the amplifier.
Configure the BIASB and BIASA pins as shown in Figure 41 with RBIAS controlling IDD as illustrated in Figure 42. Keep the
network of passive components between BIASB and VDD close to the device package to minimize parasitic.
EPAD
Exposed Pad. Solder the exposed paddle to a low impedance electrical and thermal ground plane.



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