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TC6320TG 数据表(PDF) 3 Page - Supertex, Inc

部件名 TC6320TG
功能描述  N- and P-Channel Enhancement-Mode MOSFET Pair
PDF  3 Pages
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制造商  SUTEX [Supertex, Inc]
网页  http://www.supertex.com
标志 SUTEX - Supertex, Inc

TC6320TG 数据表(HTML) 3 Page - Supertex, Inc

  TC6320TG Datasheet HTML 1Page - Supertex, Inc TC6320TG Datasheet HTML 2Page - Supertex, Inc TC6320TG Datasheet HTML 3Page - Supertex, Inc  
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TC6320
________________________________________________________________________________
P-Channel Electrical Characteristics (at TA=25°C unless otherwise specified)
Symbol
Parameter
Min
Typ
Max
Units
Conditions
BVDSS
Drain-to-Source
Breakdown Voltage
-200
V
VGS=0V, ID=-2mA
VGS(th)
Gate Threshold Voltage
-1.0
-2.4
V
VGS=VDS, ID=-1mA
∆VGS(th)
Change in VGS(th) with Temperature
4.5
mV/°C
VGS=VDS, ID=-1mA
RGS
Gate-Source Shunt Resistor
10
50
K
IGS=-100µA
∆RGS
Change in RGS with Temperature
TBD
%/°C
IGS=-100µA
VzGS
Gate-Source Zener Voltage
13.2
25
V
IGS=-2mA
∆VGS(th)
Change in VzGS with Temperature
TBD
mV/°C
IGS=-2mA
-10
µA
VGS=0V, VDS=Max Rating
IDSS
Zero Gate Voltage Drain Current
-1.0
mA
VGS=0V, VDS=0.8 Max
Rating, TA=125°C
-1.0
VGS=-4.5V, VDS=-25V
ID(ON)
On-State Drain Current
-2.0
A
VGS=-10V, VDS=-25V
10
VGS=-4.5V, ID=-150mA
RDS(ON)
Static Drain-to-Source
ON-State Resistance
8.0
VGS=-10V, ID=-1.0A
∆RDS(ON) Change in RDS(ON) with Temperature
1.0
%/°C
VGS=-10V, ID=-200mA
GFS
Forward Transconductance
400
mmho
VDS=-25V, ID=-200mA
CISS
Input Capacitance
200
COSS
Common Source Output Capacitance
55
CRSS
Reverse Transfer Capacitance
30
pF
VGS=0V, VDS=-25V
f=1MHz
td(ON)
Turn-ON Delay Time
10
tr
Rise Time
15
td(OFF)
Turn-Off Delay Time
20
tf
Fall Time
15
ns
VDD=-25V,
ID=-1.0A
RGEN=25
VSD
Diode Forward Voltage Drop
-1.8
V
VGS=0V, ISD=-0.5A
trr
Reverse Recovery Time
300
ns
VGS=0V, ISD=-0.5A
Notes:
1) All DC parameters 100% tested at 25°C unless otherwise stated. (Pulsed test: 300µs pulse at 2% duty cycle.)
2) All AC parameters sample tested.
P-Channel Switching Waveforms and Test Circuit
RGEN
Input
Pulse
Generator
VDD
RL
D.U.T
OUTPUT
0V
-10V
0V
V
DD
td(OFF)
Input
Output
tr
tf
td(ON)
t(ON)
t(OFF)
90%
10%
90%
10%
10%
90%
1/22/03



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