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Data Sheet

ADCA5190

APPLICATIONS INFORMATION

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Rev. 0 | 16 of 22

SUPPLY VOLTAGE AND BIAS CURRENT

The ADCA5190 provides flexible options for biasing for various ap-

plications. The voltage can be adjusted from 5 V to 8 V depending

on the RF demand and the available supplies. The bias current

can be adjusted between 200 mA and 450 mA to optimize power

consumption and linearity for a given application. The RSET pin

(Pin 20) can also be used to optimize performance for a given

supply voltage.

There are several options for setting the bias current, IDD, of the

ADCA5190. The passive bias approach is the most basic and

provides a dc voltage at the RF inputs, RFIP (Pin 2 and Pin 3) and

RFIN (Pin 6 and Pin 7), that is generated from a resistor divider (R4

and R3) off the VDD supply rail, as seen in Figure 31. The output

voltage of the resistor divider, VBIAS_ADJ, is connected through a

ferrite bead (E1) to the ac ground terminal of T1. This voltage

also sets the dc bias at the outputs of T1, which drive the RF

inputs. The typical relationship between VBIAS_ADJ and IDD is shown

in Figure 30. This approach requires the fewest components, but

process variation results in the bias current varying ~±15% from

the typical IDD value. This also affects device performance similarly

to intentionally adjusting the current of a nominal device. Noise or

variation on the VDD supply also directly affects the bias current.

In applications where some variation in performance is acceptable,

this simple approach to biasing is ideal.

If more tightly controlled bias current is desired, there are several

options available. When supply voltage imprecision is a concern,

adding a voltage reference diode, such as the ADR5041 to develop

the gate voltages, removes bias current dependence on the supply

rail. If process variation is a concern, there is a simple and low

cost analog circuit employing matched PNP devices that can be

used to compensate for the vast majority of process variation in the

ADCA5190. This circuit is referred to as active biasing. A schematic

for such a circuit is provided in Figure 32. The values of the three

resistors (R2, R13, and R15) surrounding the dual PNP (Q1) vary

depending on the supply voltage and target current. Values for

two typical bias targets are supplied in Table 9, but the same

approach can be used for any supply voltage and current combina-

tion desired. If the target application already has a digital-to-analog

converter (DAC) available with an extra output, driving the voltage

at Pin 1 of E1 in Downstream Cable Application Circuit with Passive

Biasing Bill of Materials, and monitoring IDD, allows the user to

precisely servo the targeted IDD level.

In both the passive and active biasing approaches, performance

is optimized by setting the voltage at the RSET pin (Pin 20). This

voltage can be pulled up or down by selecting the values of R8 and

R20, as shown in Table 8.

Figure 30. IDD vs. VBIAS_ADJ

Table 8. Suggested Values for R8 and R20 vs. VDD 1

VDD

R20

5.0 V

DNP

6490 Ω

6.0 V

10 kΩ

DNP

7.0 V

3.16 kΩ

DNP

8.0 V

2 kΩ

DNP

1 DNP means do not populate.

Table 9. Suggested Values for R2, R13, and R15 vs. Bias Target

Configuration

R13

R15

VDD = 8 V, IDD = 375 mA

5110 Ω

44,200 Ω

1180 Ω

VDD = 5 V, IDD = 250 mA

7150 Ω

49,900 Ω

1500 Ω

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