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SWCS049A 数据表(PDF) 65 Page - Texas Instruments |
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SWCS049A 数据表(HTML) 65 Page - Texas Instruments |
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65 / 144 page  65 TPS65911 www.ti.com SWCS049S – JUNE 2010 – REVISED AUGUST 2018 Submit Documentation Feedback Product Folder Links: TPS65911 Detailed Description Copyright © 2010–2018, Texas Instruments Incorporated Table 6-5. Interrupt Sources (continued) INTERRUPT DESCRIPTION HOT_DIE_IT The embedded thermal monitoring module has detected a die temperature above the hot-die detection threshold (running in ACTIVE and SLEEP state). Level sensitive interrupt. PWRHOLD_R_IT PWRHOLD signal rising edge PWRHOLD_F_IT PWRHOLD signal falling-edge PWRON_LP_IT PWRON is low during more than the long-press delay: PWON_TO_OFF_DELAY (can be disabled though register programming). PWRON_IT PWRON is low while the device is on (running in ACTIVE and SLEEP state). Level-sensitive interrupt. VMBHI_IT The battery voltage rise above the VMBHI threshold: NO SUPPLY-to-OFF or BACKUP-to- OFF device states transition (first battery plug or battery voltage bounce detection) VMBDCH_IT The battery voltage fall down below the VMBDCH threshold: the minimum operating voltage of power supplies. GPIO0_R_IT GPIO_CKSYNC rising-edge detection GPIO0_F_IT GPIO_CKSYNC falling-edge detection VMBCH2_H_IT Comparator 2 input above threshold detection VMBCH2_L_IT Comparator 2 input below threshold detection GPIO1_R_IT GPIO1 rising-edge detection GPIO1_F_IT GPIO1 falling-edge detection GPIO2_R_IT GPIO2 rising-edge detection GPIO2_F_IT GPIO2 falling-edge detection GPIO3_R_IT GPIO3 rising-edge detection GPIO3_F_IT GPIO3 falling-edge detection GPIO4_R_IT GPIO4 rising-edge detection GPIO4_F_IT GPIO4 falling-edge detection GPIO5_R_IT GPIO5 rising-edge detection GPIO5_F_IT GPIO5 falling-edge detection WTCHDG_IT Watchdog interrupt PWRDN_IT PWRDN reset interrupt 6.15 Register Maps 6.15.1 Functional Registers The possible device reset domains are: • Full reset: All digital logic of device is reset. – Caused by POR (power on reset) when VCC7 < VBNPR and BB < VBNPR • General reset: No impact on RTC, backup registers or interrupt status. – Caused by PWON_LP_RST bit set high or – DEV_OFF_RST bit set high or – HDRST input set high • Turnoff OFF: Power reinitialization in off/backup mode. In the following register description, the reset domain for each register is defined in the register table heading. NOTE DCDCCTRL_REG and DEVCTRL2_REG have bits in two reset domains. The comment Default value: See boot configuration indicates that bit default value is set in boot configuration and not by the register reset value. |
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