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SWCS049A 数据表(PDF) 104 Page - Texas Instruments |
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SWCS049A 数据表(HTML) 104 Page - Texas Instruments |
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104 / 144 page  104 TPS65911 SWCS049S – JUNE 2010 – REVISED AUGUST 2018 www.ti.com Submit Documentation Feedback Product Folder Links: TPS65911 Detailed Description Copyright © 2010–2018, Texas Instruments Incorporated Table 6-66. INT_STS_REG Address Offset 0x50 Instance Reset Domain: FULL RESET Description Interrupt status register: The interrupt status bit is set to 1 when the associated interrupt event is detected. Interrupt status bit is cleared by writing 1. Type RW 7 6 5 4 3 2 1 0 RTC_PERIOD_ IT RTC_ALARM_ IT HOTDIE_IT PWRHOLD_R_ IT PWRON_LP_IT PWRON_IT VMBHI_IT PWRHOLD_F_ IT Bits Field Name Description Type Reset 7 RTC_PERIOD_IT RTC period event interrupt status. RW W1 to Clr 0 6 RTC_ALARM_IT RTC alarm event interrupt status. RW W1 to Clr 0 5 HOTDIE_IT Hot-die event interrupt status. RW W1 to Clr 0 4 PWRHOLD_R_IT Rising PWRHOLD event interrupt status. RW W1 to Clr 0 3 PWRON_LP_IT PWRON Long Press event interrupt status. RW W1 to Clr 0 2 PWRON_IT PWRON event interrupt status. RW W1 to Clr 0 1 VMBHI_IT VBAT > VMHI event interrupt status RW W1 to Clr 0 0 PWRHOLD_F_IT Falling PWRHOLD event interrupt status. RW W1 to Clr 0 |
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