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SWCS049B 数据表(PDF) 102 Page - Texas Instruments |
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SWCS049B 数据表(HTML) 102 Page - Texas Instruments |
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102 / 144 page  102 TPS65911 SWCS049S – JUNE 2010 – REVISED AUGUST 2018 www.ti.com Submit Documentation Feedback Product Folder Links: TPS65911 Detailed Description Copyright © 2010–2018, Texas Instruments Incorporated Table 6-64. EN2_LDO_ASS_REG Address Offset 0x47 Instance Reset Domain: TURNOFF RESET Description Configuration Register setting the LDO regulators, driven by the multiplexed SDASR_EN2 signal. When control bit = 1, LDO regulator state is driven by the SDASR_EN2 control signal and is also defined though SLEEP_KEEP_LDO_ON register setting: When SDASR_EN2 is high the regulator is on, When SCLSR_EN2 is low: - the regulator is off if its corresponding Control bit = 0 in SLEEP_KEEP_LDO_ON register - the regulator is working in low-power mode if its corresponding control bit = 1 in SLEEP_KEEP_LDO_ON register When control bit = 0 no effect: LDO regulator state is driven though registers programming and the device state Any control bit of this register set to 1 will disable the I2C SR Interface functionality Type RW 7 6 5 4 3 2 1 0 LDO3_EN2 LDO4_EN2 LDO7_EN2 LDO8_EN2 LDO5_EN2 LDO2_EN2 LDO1_EN2 LDO6_EN2 Bits Field Name Description Type Reset 7 LDO3_EN2 Setting supply state control though SDASR_EN2 signal RW 0 6 LDO4_EN2 Setting supply state control though SDASR_EN2 signal RW 0 5 LDO7_EN2 Setting supply state control though SDASR_EN2 signal RW 0 4 LDO8_EN2 Setting supply state control though SDASR_EN2 signal RW 0 3 LDO5_EN2 Setting supply state control though SDASR_EN2 signal RW 0 2 LDO2_EN2 Setting supply state control though SDASR_EN2 signal RW 0 1 LDO1_EN2 Setting supply state control though SDASR_EN2 signal RW 0 0 LDO6_EN2 Setting supply state control though SDASR_EN2 signal RW 0 |
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