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SWCS049B 数据表(PDF) 105 Page - Texas Instruments |
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SWCS049B 数据表(HTML) 105 Page - Texas Instruments |
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105 / 144 page  105 TPS65911 www.ti.com SWCS049S – JUNE 2010 – REVISED AUGUST 2018 Submit Documentation Feedback Product Folder Links: TPS65911 Detailed Description Copyright © 2010–2018, Texas Instruments Incorporated Table 6-67. INT_MSK_REG Address Offset 0x51 Instance Reset Domain: GENERAL RESET Description Interrupt mask register: When *_IT_MSK is set to 1, the associated interrupt is masked: INT1 signal is not activated, but *_IT interrupt status bit is updated. When *_IT_MSK is set to 0, the associated interrupt is enabled: INT1 signal is activated, *_IT is updated. Type RW 7 6 5 4 3 2 1 0 RTC_PERIOD_ IT_MSK RTC_ALARM_ IT_MSK HOTDIE_ IT_MSK PWRHOLD_R_ IT_MSK PWRON_LP_ IT_MSK PWRON_ IT_MSK VMBHI_ IT_MSK PWRHOLD_F_ IT_MSK Bits Field Name Description Type Reset 7 RTC_PERIOD_IT_MS K RTC period event interrupt mask. RW 1 6 RTC_ALARM_IT_MS K RTC alarm event interrupt mask. RW 1 5 HOTDIE_IT_MSK Hot die event interrupt mask. RW 1 4 PWRHOLD_R_IT_MS K PWRHOLD rising-edge event interrupt mask. RW 1 3 PWRON_LP_IT_MSK PWRON Long Press event interrupt mask. RW 1 2 PWRON_IT_MSK PWRON event interrupt mask. RW 1 1 VMBHI_IT_MSK VBAT > VMBHI interrupt event mask bit When 0, interrupt not masked. Device automatically switches on at NO SUPPLY-to-OFF BACKUP-to-OFF transition When 1, interrupt is masked. Device does not switch on until a start reason is received. (EEPROM bit. Default value: See boot configuration) RW 1 0 PWRHOLD_F_IT_MS K PWRHOLD falling-edge event interrupt mask. RW 1 |
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