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SWCS049B 数据表(PDF) 106 Page - Texas Instruments |
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SWCS049B 数据表(HTML) 106 Page - Texas Instruments |
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106 / 144 page  106 TPS65911 SWCS049S – JUNE 2010 – REVISED AUGUST 2018 www.ti.com Submit Documentation Feedback Product Folder Links: TPS65911 Detailed Description Copyright © 2010–2018, Texas Instruments Incorporated Table 6-68. INT_STS2_REG Address Offset 0x52 Instance Reset Domain: FULL RESET Description Interrupt status register: The interrupt status bit is set to 1 when the associated interrupt event is detected. Interrupt status bit is cleared by writing 1. Type RW 7 6 5 4 3 2 1 0 GPIO3_F_IT GPIO3_R_IT GPIO2_F_IT GPIO2_R_IT GPIO1_F_IT GPIO1_R_IT GPIO0_F_IT GPIO0_R_IT Bits Field Name Description Type Reset 7 GPIO3_F_IT GPIO3 falling-edge detection interrupt status RW W1 to Clr 0 6 GPIO3_R_IT GPIO3 rising-edge detection interrupt status RW W1 to Clr 0 5 GPIO2_F_IT GPIO2 falling-edge detection interrupt status RW W1 to Clr 0 4 GPIO2_R_IT GPIO2 rising-edge detection interrupt status RW W1 to Clr 0 3 GPIO1_F_IT GPIO1 falling-edge detection interrupt status RW W1 to Clr 0 2 GPIO1_R_IT GPIO1 rising-edge detection interrupt status RW W1 to Clr 0 1 GPIO0_F_IT GPIO0 falling-edge detection interrupt status RW W1 to Clr 0 0 GPIO0_R_IT GPIO0 rising-edge detection interrupt status RW W1 to Clr 0 Table 6-69. INT_MSK2_REG Address Offset 0x53 Instance Reset Domain: GENERAL RESET Description Interrupt mask register: When *_IT_MSK is set to 1, the associated interrupt is masked: INT1 signal is not activated, but *_IT interrupt status bit is updated. When *_IT_MSK is set to 0, the associated interrupt is enabled: INT1 signal is activated, *_IT is updated. Type RW 7 6 5 4 3 2 1 0 GPIO3_F_ IT_MSK GPIO3_R_ IT_MSK GPIO2_F_ IT_MSK GPIO2_R_ IT_MSK GPIO1_F_ IT_MSK GPIO1_R_ IT_MSK GPIO0_F_ IT_MSK GPIO0_R_ IT_MSK Bits Field Name Description Type Reset 7 GPIO3_F_IT_MSK GPIO3 falling-edge detection interrupt mask. RW 1 6 GPIO3_R_IT_MSK GPIO3 rising-edge detection interrupt mask. RW 1 5 GPIO2_F_IT_MSK GPIO2 falling-edge detection interrupt mask. RW 1 4 GPIO2_R_IT_MSK GPIO2 rising-edge detection interrupt mask. RW 1 3 GPIO1_F_IT_MSK GPIO1 falling-edge detection interrupt mask. RW 1 2 GPIO1_R_IT_MSK GPIO1 rising-edge detection interrupt mask. RW 1 1 GPIO0_F_IT_MSK GPIO0 falling-edge detection interrupt mask. RW 1 0 GPIO0_R_IT _MSK GPIO0 rising-edge detection interrupt mask. RW 1 |
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