数据搜索系统,热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

AD9515/PCBZ 数据表(PDF) 4 Page - Analog Devices

部件名 AD9515/PCBZ
功能描述  1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Two Outputs
PDF  28 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD9515/PCBZ 数据表(HTML) 4 Page - Analog Devices

  AD9515/PCBZ Datasheet HTML 1Page - Analog Devices AD9515/PCBZ Datasheet HTML 2Page - Analog Devices AD9515/PCBZ Datasheet HTML 3Page - Analog Devices AD9515/PCBZ Datasheet HTML 4Page - Analog Devices AD9515/PCBZ Datasheet HTML 5Page - Analog Devices AD9515/PCBZ Datasheet HTML 6Page - Analog Devices AD9515/PCBZ Datasheet HTML 7Page - Analog Devices AD9515/PCBZ Datasheet HTML 8Page - Analog Devices AD9515/PCBZ Datasheet HTML 9Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 4 / 28 page
background image
AD9515
Data Sheet
Rev. B | Page 4 of 28
TIMING CHARACTERISTICS
CLK input slew rate = 1 V/ns or greater.
Table 3.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
LVPECL
Termination = 50 Ω to VS − 2 V
Output Rise Time, tRP
60
100
ps
20% to 80%, measured differentially
Output Fall Time, tFP
60
100
ps
80% to 20%, measured differentially
PROPAGATION DELAY, tPECL, CLK-TO-LVPECL OUT
Divide = 1
355
480
635
ps
Divide = 2 − 32
395
530
710
ps
Variation with Temperature
0.5
ps/°C
OUTPUT SKEW, LVPECL OUTPUT
LVPECL OUT Across Multiple Parts, tSKP_AB31
125
ps
LVDS
Termination = 100 Ω differential
Output Rise Time, tRL
200
350
ps
20% to 80%, measured differentially
Output Fall Time, tFL
210
350
ps
80% to 20%, measured differentially
PROPAGATION DELAY, tLVDS, CLK-TO-LVDS OUT
Delay off on OUT4
OUT3 to OUT4
Divide = 1
1.00
1.25
1.55
ns
Divide = 2 − 32
1.05
1.30
1.60
ns
Variation with Temperature
0.9
ps/°C
OUTPUT SKEW, LVDS OUTPUT
Delay off on OUT4
LVDS OUT Across Multiple Parts, tSKV_AB1
230
ps
CMOS
B outputs are inverted; termination = open
Output Rise Time, tRC
650
865
ps
20% to 80%; CLOAD = 3 pF
Output Fall Time, tFC
650
990
ps
80% to 20%; CLOAD = 3 pF
PROPAGATION DELAY, tCMOS, CLK-TO-CMOS OUT
Delay off on OUT4
Divide = 1
1.10
1.45
1.75
ns
Divide = 2 − 32
1.15
1.50
1.80
ns
Variation with Temperature
1
ps/°C
OUTPUT SKEW, CMOS OUTPUT
Delay off on OUT4
CMOS OUT Across Multiple Parts, tSKC_AB1
300
ps
LVPECL-TO-LVDS OUT
Everything the same; different logic type
Output Delay, tSKP_V
700
970
1150
ps
LVPECL to LVDS on same part
LVPECL-TO-CMOS OUT
Everything the same; different logic type
Output Delay, tSKP_C
0.88
1.14
1.43
ns
LVPECL to CMOS on same part
DELAY ADJUST (OUT2; LVDS AND CMOS)
S0 = 1/3
Zero Scale Delay Time2
0.34
ns
Zero Scale Variation with Temperature
0.20
ps/°C
Full Scale Time Delay2
1.7
ns
Full Scale Variation with Temperature
−0.38
ps/°C
S0 = 2/3
Zero Scale Delay Time2
0.45
ns
Zero Scale Variation with Temperature
0.31
ps/°C
Full Scale Time Delay2
5.9
ns
Full Scale Variation with Temperature
−1.3
ps/°C



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com