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AD9515/PCBZ 数据表(PDF) 20 Page - Analog Devices

部件名 AD9515/PCBZ
功能描述  1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Two Outputs
PDF  28 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD9515/PCBZ 数据表(HTML) 20 Page - Analog Devices

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AD9515
Data Sheet
Rev. B | Page 20 of 28
PROGRAMMING
Table 10. S0—OUT1 Delay Full Scale
S0
Delay
0
Bypassed
1/3
1.5 ns
2/3
5 ns
1
10 ns
Table 11. S1—Output Logic Configuration
S1
OUT0
OUT1
0
LVPECL 790 mV
LVDS
1/3
LVPECL 400 mV
LVDS
2/3
LVPECL 790 mV
CMOS
1
LVPECL 400 mV
CMOS
Table 12. S2, S3, and S4—OUT0
S2
S3
S4
OUT0
Divide (Duty Cycle1)
OUT0
Phase
0
0
0
1
0
1/3
0
0
2 (50%)
0
2/3
0
0
3 (33%)
0
1
0
0
4 (50%)
0
0
1/3
0
5 (40%)
0
1/3
1/3
0
6 (50%)
0
2/3
1/3
0
7 (43%)
0
1
1/3
0
8 (50%)
0
0
2/3
0
9 (44%)
0
1/3
2/3
0
10 (50%)
0
2/3
2/3
0
11 (45%)
0
1
2/3
0
12 (50%)
0
0
1
0
OUT0 OFF
1/3
1
0
14 (50%)
0
2/3
1
0
15 (47%)
0
1
1
0
16 (50%)
0
0
0
1/3
17 (47%)
0
1/3
0
1/3
18 (50%)
0
2/3
0
1/3
19 (47%)
0
1
0
1/3
20 (50%)
0
0
1/3
1/3
21 (48%)
0
1/3
1/3
1/3
22 (50%)
0
2/3
1/3
1/3
23 (48%)
0
1
1/3
1/3
24 (50%)
0
0
2/3
1/3
25 (48%)
0
S2
S3
S4
OUT0
Divide (Duty Cycle1)
OUT0
Phase
1/3
2/3
1/3
26 (50%)
0
2/3
2/3
1/3
27 (48%)
0
1
2/3
1/3
28 (50%)
0
0
1
1/3
29 (48%)
0
1/3
1
1/3
30 (50%)
0
2/3
1
1/3
31 (48%)
0
1
1
1/3
32 (50%)
0
0
0
2/3
2 (50%)
1
1/3
0
2/3
4 (50%)
1
2/3
0
2/3
4 (50%)
2
1
0
2/3
4 (50%)
3
0
1/3
2/3
8 (50%)
1
1/3
1/3
2/3
8 (50%)
2
2/3
1/3
2/3
8 (50%)
3
1
1/3
2/3
8 (50%)
4
0
2/3
2/3
8 (50%)
5
1/3
2/3
2/3
8 (50%)
6
2/3
2/3
2/3
8 (50%)
7
1
2/3
2/3
16 (50%)
1
0
1
2/3
16 (50%)
2
1/3
1
2/3
16 (50%)
3
2/3
1
2/3
16 (50%)
4
1
1
2/3
16 (50%)
5
0
0
1
16 (50%)
6
1/3
0
1
16 (50%)
7
2/3
0
1
16 (50%)
8
1
0
1
16 (50%)
9
0
1/3
1
16 (50%)
10
1/3
1/3
1
16 (50%)
11
2/3
1/3
1
16 (50%)
12
1
1/3
1
16 (50%)
13
0
2/3
1
16 (50%)
14
1/3
2/3
1
16 (50%)
15
2/3
2/3
1
32 (50%)
1
1
2/3
1
32 (50%)
2
0
1
1
32 (50%)
3
1/3
1
1
32 (50%)
4
2/3
1
1
32 (50%)
5
1
1
1
Do not use
1 Duty cycle is the clock signal high time divided by the total period.



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