ADP5589ACPZ-01-R7 datasheet(43/52 Pages) AD

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Data Sheet

ADP5589

Rev. B | Page 43 of 52

CLOCK_DIV_CFG Register 0x43

Table 75. CLOCK_DIV_CFG Bit Descriptions

Bits

Name

R/W

Description

Reserved.

CLK_INV

R/W

Inverts the divided down clock signal.

[5: 1]

CLK_DIV[4:0]

R/W

Defines the divide down scale of the externally supplied clock.

00000 = divide by 1 (pass-through).

00001 = divide by 2.

00010 = divide by 3.

00011 = divide by 4.

11111 = divide by 32.

CLK_DIV_EN

R/W

Enables the clock divider circuit to divide down the externally supplied clock signal.

LOGIC_1_CFG Register 0x44

Table 76. LOGIC_1_CFG Bit Descriptions

Bits

Name

R/W

Description

Reserved.

LY1_INV

R/W

0 = LY1 output not inverted before passing into Logic Block 1.

1 = inverts output LY1 from Logic Block 1.

LC1_INV

R/W

0 = LC1 input not inverted before passing into Logic Block 1.

1 = inverts input LC1 before passing it into Logic Block 1.

LB1_INV

R/W

0 = LB1 input not inverted before passing into Logic Block 1.

1 = inverts input LB1 before passing it into Logic Block 1.

LA1_INV

R/W

0 = LA1 input not inverted before passing into Logic Block 1.

1 = inverts input LA1 before passing it into Logic Block 1.

[2: 0]

LOGIC1_SEL[2:0]

R/W

Configures the digital mux for Logic Block 1.

000 = off/disable.

001 = AND1.

010 = OR1.

011 = XOR1.

100 = FF1.

101 = IN_LA1.

110 = IN_LB1.

111 = IN_LC1.

LOGIC_2_CFG Register 0x45

Table 77. LOGIC_2_CFG Bit Descriptions

Bits

Name

R/W

Description

LY1_CASCADE

R/W

0 = use Input LA2 for Logic Block 2.

1 = use Output LY1 from Logic Block 1 instead of LA2 as the input for Logic Block 2.

The R0 pin can be used as GPIO or key when cascade is in use.

LY2_INV

R/W

0 = LY2 input not inverted before passing into Logic Block 2.

1 = inverts Output LY2 from Logic Block 2.

LC2_INV

R/W

0 = LC2 input not inverted before passing into Logic Block 2.

1 = inverts Input LC2 before passing it into Logic Block 2.

LB2_INV

R/W

0 = LB2 input not inverted before passing into Logic Block 2.

1 = inverts Input LB2 before passing it into Logic Block 2.

LA2_INV

R/W

0 = LA2 input not inverted before passing into Logic Block 2.

1 = inverts Input LA2 before passing it into Logic Block 2.

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