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AM6441...ALV 数据表(PDF) 24 Page - Texas Instruments

部件名 AM6441...ALV
功能描述  AM64x Sitara™ Processors
PDF  244 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

AM6441...ALV 数据表(HTML) 24 Page - Texas Instruments

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Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
NUMBER [1]
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
SIGNAL NAME [3]
MUX
MODE
[4]
TYPE
[5]
DSIS
[6]
BALL
STATE
DURING
RESET
RX/TX/PULL [7]
BALL
STATE
AFTER
RESET
RX/TX/PULL [8]
MUX
MODE
AFTER
RESET
[9]
I/O
OPERATING
VOLTAGE [10]
POWER [11]
HYS
[12]
BUFFER
TYPE [13]
PULL
UP/DOWN
TYPE [14]
T17
GPMC0_AD9
PADCONFIG:
PADCONFIG24
0x000F4060
GPMC0_AD9
0
IO
0
On / Off / Off
On / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
FSI_RX0_D0
1
I
0
UART3_CTSn
2
I
1
EHRPWM2_B
3
IO
0
TRC_DATA7
6
O
GPIO0_24
7
IO
pad
PRG0_PWM2_B2
9
IO
1
BOOTMODE09
Bootstrap
I
R16
GPMC0_AD10
PADCONFIG:
PADCONFIG25
0x000F4064
GPMC0_AD10
0
IO
0
On / Off / Off
On / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
FSI_RX0_D1
1
I
0
UART4_CTSn
2
I
1
EHRPWM_TZn_IN2
3
I
0
EHRPWM8_B
4
IO
0
TRC_DATA8
6
O
GPIO0_25
7
IO
pad
PRG1_PWM2_B2
9
IO
1
BOOTMODE10
Bootstrap
I
W20
GPMC0_AD11
PADCONFIG:
PADCONFIG26
0x000F4068
GPMC0_AD11
0
IO
0
On / Off / Off
On / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
FSI_RX1_CLK
1
I
0
UART5_CTSn
2
I
1
EQEP1_A
3
I
0
TRC_DATA9
6
O
GPIO0_26
7
IO
pad
EHRPWM7_A
8
IO
0
BOOTMODE11
Bootstrap
I
W21
GPMC0_AD12
PADCONFIG:
PADCONFIG27
0x000F406C
GPMC0_AD12
0
IO
0
On / Off / Off
On / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
FSI_RX1_D0
1
I
0
UART6_CTSn
2
I
1
EQEP1_B
3
I
0
TRC_DATA10
6
O
GPIO0_27
7
IO
pad
EHRPWM7_B
8
IO
0
BOOTMODE12
Bootstrap
I
AM6442, AM6441, AM6421, AM6412, AM6411
SPRSP56D – JANUARY 2021 – REVISED JULY 2022
www.ti.com
24
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Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: AM6442 AM6441 AM6421 AM6412 AM6411



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