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Table 7-33. CPSW3G RGMII1 IOSETs (continued)

SIGNALS

IOSET1

IOSET2

BALL NAME

MUXMODE

BALL NAME

MUXMODE

RGMII1_RD0

PRG0_PRU1_GPO7

PRG1_PRU1_GPO5

RGMII1_RD1

PRG0_PRU1_GPO9

PRG1_PRU1_GPO8

RGMII1_RD2

PRG0_PRU1_GPO10

PRG1_PRU1_GPO18

RGMII1_RD3

PRG0_PRU1_GPO17

PRG1_PRU1_GPO19

7.10.5.2 DDRSS

For more details about features and additional description information on the device (LP)DDR4 Memory

Interface, see the corresponding subsections within Signal Descriptions and Detailed Description sections.

Table 7-34 and Figure 7-28 present switching characteristics for DDRSS.

Table 7-34. DDRSS Switching Characteristics

see Figure 7-28

NO.

PARAMETER

DDR TYPE

MIN

MAX

UNIT

tc(DDR_CKP/

DDR_CKN)

Cycle time, DDR_CKP and DDR_CKN

LPDDR4

1.25(1)

DDR4

1.25(1)

1.6

(1)

Minimum DDR clock Cycle time will be limited based on the specific memory type (vendor) used in a system and by PCB

implementation. Refer to AM64x\AM243x DDR Board Design and Layout Guidelines for the proper PCB implementation to achieve

maximum DDR frequency.

DDR0_CKP

DDR0_CKN

Figure 7-28. DDRSS Switching Characteristics

For more information, see DDR Subsystem (DDRSS) section in Memory Controllers chapter in the device TRM.

7.10.5.3 ECAP

Table 7-35, Table 7-36, Figure 7-29, Table 7-37, and Figure 7-30 present timing conditions, requirements, and

switching characteristics for ECAP.

Table 7-35. ECAP Timing Conditions

PARAMETER

MIN

MAX

UNIT

INPUT CONDITIONS

SRI

Input slew rate

V/ns

OUTPUT CONDITIONS

Output load capacitance

AM6442, AM6441, AM6421, AM6412, AM6411

SPRSP56D – JANUARY 2021 – REVISED JULY 2022

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