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AM6421...ALV 数据表(PDF) 140 Page - Texas Instruments |
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AM6421...ALV 数据表(HTML) 140 Page - Texas Instruments |
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140 / 244 page  Table 7-42. EQEP Timing Requirements (continued) see Figure 7-35 NO. PARAMETER DESCRIPTION MIN MAX UNIT QEP3 tw(QEPIL) Pulse duration, QEP_I low 2 + 2P (1) ns QEP4 tw(QEPSH) Pulse duration, QEP_S high 2 + 2P (1) ns QEP5 tw(QEPSL) Pulse duration, QEP_S low 2 + 2P (1) ns (1) P = sysclk period in ns QEP_S QEP4 EPERIPHERALS_TIMNG_03 QEP_I QEP2 QEP_A/B QEP1 QEP3 QEP5 Figure 7-35. EQEP Timing Requirements Table 7-43. EQEP Switching Characteristics NO. PARAMETER DESCRIPTION MIN MAX UNIT QEP6 td(QEP-CNTR) Delay time, external clock to counter increment 24 ns For more information, see Enhanced Quadrature Encoder Pulse (EQEP) Module section in Peripherals chapter in the device TRM. 7.10.5.6 FSI Table 7-44, Table 7-45, Figure 7-36, Table 7-46, Figure 7-37, Table 7-47, and Figure 7-38 present timing conditions, requirements, and switching characteristics for FSI. Table 7-44. FSI Timing Conditions PARAMETER MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate 0.8 4 V/ns OUTPUT CONDITIONS CL Output load capacitance 1 7 pF Table 7-45. FSI Timing Requirements see Figure 7-36 NO. MIN MAX UNIT FSIR1 tc(RX_CLK) Cycle time, FSI_RXn_CLK 20 ns FSIR2 tw(RX_CLK) Pulse width, FSI_RXn_CLK low or FSI_RXn_CLK high 0.5P - 1 (1) 0.5P + 1 (1) ns FSIR3 tsu(RX_D-RX_CLK) Setup time, FSI_RXn_D[1:0] valid before FSI_RXn_CLK 3 ns AM6442, AM6441, AM6421, AM6412, AM6411 SPRSP56D – JANUARY 2021 – REVISED JULY 2022 www.ti.com 140 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: AM6442 AM6441 AM6421 AM6412 AM6411 |
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