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AM6421...ALV 数据表(PDF) 185 Page - Texas Instruments |
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AM6421...ALV 数据表(HTML) 185 Page - Texas Instruments |
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185 / 244 page  7.10.5.12.2.7 UHS–I SDR104 Mode Table 7-89, and Figure 7-77 present switching characteristics for MMC1 – UHS-I SDR104 Mode. Table 7-89. Switching Characteristics for MMC1 – UHS-I SDR104 Mode see Figure 7-77 NO. PARAMETER MIN MAX UNIT fop(clk) Operating frequency, MMC1_CLK 200 MHz SDR1045 tc(clk) Cycle time, MMC1_CLK 5 ns SDR1046 tw(clkH) Pulse duration, MMC1_CLK high 2.08 ns SDR1047 tw(clkL) Pulse duration, MMC1_CLK low 2.08 ns SDR1048 td(clkL-cmdV) Delay time, MMC1_CLK rising edge to MMC1_CMD transition 1.12 3.16 ns SDR1049 td(clkL-dV) Delay time, MMC1_CLK rising edge to MMC1_DAT[3:0] transition 1.12 3.16 ns MMC[ ]_CLK x MMC CMD [ ]_ x MMC DAT [ ]_ [3:0] x SDR1045 SDR1047 SDR1046 SDR1048 SDR1049 SDR1048 SDR1049 Figure 7-77. MMC1 – UHS-I SDR104 – Transmit Mode 7.10.5.13 CPTS Table 7-90, Table 7-91, Figure 7-78, Table 7-92, and Figure 7-79 present timing conditions, requirements, and switching characteristics for CPTS. Table 7-90. CPTS Timing Conditions PARAMETER MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate 0.5 5 V/ns OUTPUT CONDITIONS CL Output load capacitance 2 10 pF Table 7-91. CPTS Timing Requirements see Figure 7-78 NO. PARAMETER DESCRIPTION MIN MAX UNIT T1 tw(HWTSPUSHH) Pulse duration, HWnTSPUSH high 12P(1) + 2 ns T2 tw(HWTSPUSHL) Pulse duration, HWnTSPUSH low 12P(1) + 2 ns T3 tc(RFT_CLK) Cycle time, RFT_CLK 5 8 ns T4 tw(RFT_CLKH) Pulse duration, RFT_CLK high 0.45T(2) ns T5 tw(RFT_CLKL) Pulse duration, RFT_CLK low 0.45T(2) ns (1) P = functional clock period in ns. (2) T = RFT_CLK period in ns. www.ti.com AM6442, AM6441, AM6421, AM6412, AM6411 SPRSP56D – JANUARY 2021 – REVISED JULY 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 185 Product Folder Links: AM6442 AM6441 AM6421 AM6412 AM6411 |
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