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AM6421...ALV 数据表(PDF) 186 Page - Texas Instruments |
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AM6421...ALV 数据表(HTML) 186 Page - Texas Instruments |
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186 / 244 page  RFT_CLK T3 T4 T5 HWn_TSPUSH T1 T2 Figure 7-78. CPTS Timing Requirements Table 7-92. CPTS Switching Characteristics see Figure 7-79 NO. PARAMETER DESCRIPTION SOURCE MIN MAX UNIT T6 tw(TS_COMPH) Pulse duration, TS_COMP high 36P(1) - 2 ns T7 tw(TS_COMPL) Pulse duration, TS_COMP low 36P(1) - 2 ns T8 tw(TS_SYNCH) Pulse duration, TS_SYNC high 36P(1) - 2 ns T9 tw(TS_SYNCL) Pulse duration, TS_SYNC low 36P(1) - 2 ns T10 tw(SYNC_OUTH) Pulse duration, SYNCn_OUT high TS_SYNC 36P(1) - 2 ns GENF 5P(1) - 2 ns T11 tw(SYNC_OUTL) Pulse duration, SYNCn_OUT low TS_SYNC 36P(1) - 2 ns GENF 5P(1) - 2 ns (1) P = functional clock period in ns. TS_COMP T6 T7 TS_SYNC T8 T9 SYNCn_OUT T10 T11 Figure 7-79. CPTS Switching Characteristics For more information, see Data Movement Architecture (DMA) chapter in the device TRM. 7.10.5.14 OSPI OSPI0 offers two data capture modes, PHY mode and Tap mode. PHY mode uses an internal reference clock to transmit and receive data via a DLL based PHY, where each reference clock cycle produces a single cycle of OSPI0_CLK for Single Data Rate (SDR) transfers or a half cycle of OSPI0_CLK for Double Data Rate (DDR) transfers. PHY mode supports four clocking topologies for the receive data capture clock. Internal PHY Loopback - uses the internal reference clock as the PHY receive data capture clock. Internal Pad Loopback - uses OSPI0_LBCLKO looped back into the PHY from the OSPI0_LBCLKO pin as the PHY receive data capture clock. External Board Loopback - uses OSPI0_LBCLKO looped back into the PHY from the OSPI0_DQS pin as the PHY receive data capture clock. DQS - uses the DQS output from the attached device as the PHY receive data capture clock. SDR transfers are not supported when using the Internal Pad Loopback and DQS clocking topologies. DDR transfers are not supported when using the Internal PHY Loopback or Internal Pad Loopback clocking topologies. Tap mode uses an internal reference clock with selectable taps to adjusted data transmit and receive capture delays relative to OSPI0_CLK, which is a divide by 4 of the internal reference clock for SDR transfers or a divide AM6442, AM6441, AM6421, AM6412, AM6411 SPRSP56D – JANUARY 2021 – REVISED JULY 2022 www.ti.com 186 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: AM6442 AM6441 AM6421 AM6412 AM6411 |
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