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AM6421...ALV 数据表(PDF) 204 Page - Texas Instruments |
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AM6421...ALV 数据表(HTML) 204 Page - Texas Instruments |
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204 / 244 page  MDIO3 MDIO1 MDIO2 MDIO7 MDIO4 MDIO5 MDIO[x]_MDC MDIO[x]_MDIO (input) MDIO[x]_MDIO (output) CPSW2G_MDIO_TIMING_01 Figure 7-107. PRU_ICSSG MDIO Timing Requirements and Switching Characteristics 7.10.5.16.6.2 PRU_ICSSG MII Timing Note In order to ensure the MII_G_RT I/O timing values published in the device data sheet, the PRU_ICSSG ICSSGn_CORE_CLK (where n = 0 to 1) core clock must be configured for 200 MHz, 225 MHz, or 250 MHz and the TX_CLK_DELAYn (where n = 0 or 1) bit field in the ICSSG_TXCFG0/1 register must be set to 0h (default value). Table 7-131, Table 7-132, Figure 7-108, Table 7-133, Figure 7-109, Table 7-134, Figure 7-110, Table 7-135, and Figure 7-111 present timing conditions, requirements, and switching characteristics for PRU_ICSSG MII. Table 7-131. PRU_ICSSG MII Timing Conditions PARAMETER MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate 0.9 3.6 V/ns OUTPUT CONDITIONS CL Output load capacitance 2 20 pF Table 7-132. PRU_ICSSG MII Timing Requirements – MII[x]_RX_CLK see Figure 7-108 NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT PMIR1 tc(RX_CLK) Cycle time, MII[x]_RX_CLK 10 Mbps 399.96 400.04 ns 100 Mbps 39.996 40.004 ns PMIR2 tw(RX_CLKH) Pulse Duration, MII[x]_RX_CLK High 10 Mbps 140 260 ns 100 Mbps 14 26 ns PMIR3 tw(RX_CLKL) Pulse Duration, MII[x]_RX_CLK Low 10 Mbps 140 260 ns 100 Mbps 14 26 ns AM6442, AM6441, AM6421, AM6412, AM6411 SPRSP56D – JANUARY 2021 – REVISED JULY 2022 www.ti.com 204 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: AM6442 AM6441 AM6421 AM6412 AM6411 |
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