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AM6411...ALV 数据表(PDF) 1 Page - Texas Instruments |
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AM6411...ALV 数据表(HTML) 1 Page - Texas Instruments |
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1 / 244 page  AM64x Sitara™ Processors 1 Features Processor cores: • 1× Dual 64-bit Arm® Cortex®-A53 microprocessor subsystem at up to 1.0 GHz – Dual-core Cortex-A53 cluster with 256KB L2 shared cache with SECDED ECC – Each A53 Core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection • Up to 2× Dual-core Arm® Cortex®-R5F MCU subsystems at at up to 800 MHz, integrated for real-time processing – Dual-core Arm® Cortex®-R5F supports dual- core and single-core modes – 32KB ICache, 32KB DCache and 64KB TCM per each R5F core for a total of 256KB TCM with SECDED ECC on all memories • 1× Single-core Arm® Cortex®-M4F MCU at up to 400 MHz – 256KB SRAM with SECDED ECC Industrial subsystem: • 2× gigabit Industrial Communication Subsystems (PRU_ICSSG) – Supports Profinet IRT, Profinet RT, EtherNet/IP, EtherCAT, Time-Sensitive Networking (TSN), and more – Backward compatibility with 10/100Mb PRU_ICSS – Each PRU_ICSSG contains: • 2× Ethernet ports – MII (10/100) – RGMII (10/100/1000) • 6 PRU RISC cores per PRU_ICSSG each core having: – Instruction RAM with ECC – Broadside RAM – Multiplier with optional accumulator (MAC) – CRC16/32 hardware accelerator – Byte swap for Big/Little Endian conversion – SUM32 hardware accelerator for UDP checksum – Task Manager for preemption support • Three Data RAMs with ECC • 8 banks of 30 × 32-bit register scratchpad memory • Interrupt controller and task manager • Two 64-bit Industrial Ethernet Peripherals (IEPs) for time stamping and other time synchronization functions • 18× Sigma-Delta filters – Short circuit logic – Over-current logic • 6× Multi-protocol position encoder interfaces • One Enhanced Capture Module (ECAP) • 16550-compatible UART with a dedicated 192-MHz clock to support 12-Mbps PROFIBUS Memory subsystem: • Up to 2MB of On-chip RAM (OCSRAM) with SECDED ECC: – Can be divided into smaller banks in increments of 256KB for as many as 8 separate memory banks – Each memory bank can be allocated to a single core to facilitate software task partitioning • DDR Subsystem (DDRSS) – Supports LPDDR4, DDR4 memory types – 16-Bit data bus with inline ECC – Supports speeds up to 1600 MT/s • 1× General-Purpose Memory Controller (GPMC) – 16-Bit parallel bus with 133 MHz clock or – 32-Bit parallel bus with 100 MHz clock – Error Location Module (ELM) support System on Chip (SoC) Services: • Device Management Security Controller (DMSC-L) – Centralized SoC system controller – Manages system services including initial boot, security, and clock/reset/power management – Communication with various processing units over message manager – Simplified interface for optimizing unused peripherals • Data Movement Subsystem (DMSS) – Block Copy DMA (BCDMA) – Packet DMA (PKTDMA) – Secure Proxy (SEC_PROXY) – Ring Accelerator (RINGACC) Security: • Secure boot supported – Hardware-enforced Root-of-Trust (RoT) – Support to switch RoT via backup key – Support for takeover protection, IP protection, and anti-roll back protection • Cryptographic acceleration supported AM6442, AM6441, AM6421, AM6412, AM6411 SPRSP56D – JANUARY 2021 – REVISED JULY 2022 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change without notice. |
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