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AM6411...ALV 数据表(PDF) 132 Page - Texas Instruments |
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AM6411...ALV 数据表(HTML) 132 Page - Texas Instruments |
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132 / 244 page  Table 7-24. RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RX_ER Timing Requirements – RMII Mode see Figure 7-24 NO. PARAMETER DESCRIPTION MIN MAX UNIT RMII4 tsu(RXD-REF_CLK) Setup time, RMII[x]_RXD[1:0] valid before RMII[x]_REF_CLK 4 ns tsu(CRS_DV-REF_CLK) Setup time, RMII[x]_CRS_DV valid before RMII[x]_REF_CLK 4 ns tsu(RX_ER-REF_CLK) Setup time, RMII[x]_RX_ER valid before RMII[x]_REF_CLK 4 ns RMII5 th(REF_CLK-RXD) Hold time RMII[x]_RXD[1:0] valid after RMII[x]_REF_CLK 2 ns th(REF_CLK-CRS_DV) Hold time, RMII[x]_CRS_DV valid after RMII[x]_REF_CLK 2 ns th(REF_CLK-RX_ER) Hold time, RMII[x]_RX_ER valid after RMII[x]_REF_CLK 2 ns RMII4 RMII5 RMII[x]_ _ REF CLK RMII[x]_RXD[1:0], RMII[x]_CRS_DV, RMII[x]_RX_ER Figure 7-24. CPSW3G RMII[x]_RXD[1:0], RMII[x]_CRS_DV, RMII[x]_RX_ER Timing Requirements – RMII Mode Table 7-25. RMII[x]_TXD[1:0], and RMII[x]_TX_EN Switching Characteristics – RMII Mode see Figure 7-25 NO. PARAMETER DESCRIPTION MIN MAX UNIT RMII6 td(REF_CLK-TXD) Delay time, RMII[x]_REF_CLK High to RMII[x]_ TXD[1:0] valid 2 10 ns td(REF_CLK-TX_EN) Delay time, RMII[x]_REF_CLK to RMII[x]_TX_EN valid 2 10 ns RMII[x]_TXD[1:0], RMII[x]_TX_EN RMII6 RMII[x]_REF_CLK Figure 7-25. RMII[x]_TXD[1:0], and RMII[x]_TX_EN Switching Characteristics – RMII Mode 7.10.5.1.3 CPSW3G RGMII Timing Table 7-26, Table 7-27, Table 7-28, Figure 7-26, Table 7-29, Table 7-30, and Figure 7-27 present timing conditions, requirements, and switching characteristics for CPSW3G RGMII. Table 7-26. CPSW3G RGMII Timing Conditions PARAMETER MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate 2.64 5 V/ns OUTPUT CONDITIONS CL Output load capacitance 2 20 pF PCB CONNECTIVITY REQUIREMENTS AM6442, AM6441, AM6421, AM6412, AM6411 SPRSP56D – JANUARY 2021 – REVISED JULY 2022 www.ti.com 132 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: AM6442 AM6441 AM6421 AM6412 AM6411 |
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