AM6411...ALV datasheet(190/244 Pages) TI

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Table 7-99. OSPI0 Switching Characteristics – PHY SDR Mode

see Figure 7-84

NO.

PARAMETER

MODE

MIN

MAX

UNIT

tc(CLK)

Cycle time, OSPI0_CLK

1.8V

3.3V

6.03

tw(CLKL)

Pulse duration, OSPI0_CLK low

((0.475P(1)) - 0.3)

tw(CLKH)

Pulse duration, OSPI0_CLK high

((0.475P(1)) - 0.3)

O10

td(CSn-CLK)

Delay time, OSPI0_CSn[3:0] active edge

to OSPI0_CLK rising edge

((0.475P(1)) +

(0.975M(2)R(4)) - 1)

((0.525P(1)) +

(1.025M(2)R(4)) + 1)

O11

td(CLK-CSn)

Delay time, OSPI0_CLK rising edge to

OSPI0_CSn[3:0] inactive edge

((0.475P(1)) +

(0.975N(3)R(4)) - 1)

((0.525P(1)) +

(1.025N(3)R(4)) + 1)

O12

td(CLK-D)

Delay time, OSPI0_CLK active edge to

OSPI0_D[7:0] transition

1.8V

-1.16

1.25

3.3V

-1.33

1.51

(1)

P = CLK cycle time = SCLK period in ns

(2)

M = OSPI_DEV_DELAY_REG[D_INIT_FLD]

(3)

N = OSPI_DEV_DELAY_REG[D_AFTER_FLD]

(4)

R = refclk cycle time in ns

OSPI_CLK

OSPI_TIMING_02

OSPI_CSn

O10

O11

O12

OSPI_D[i:0]

Figure 7-84. OSPI0 Switching Characteristics – PHY SDR

7.10.5.14.1.2.2 OSPI0 PHY DDR Timing

Table 7-100 defines DLL delays required for OSPI0 PHY DDR Mode. Table 7-101, Figure 7-85, Table 7-102, and

Figure 7-86 present timing requirements and switching characteristics for OSPI0 PHY DDR Mode.

Table 7-100. OSPI0 DLL Delay Mapping for PHY DDR Timing Modes

MODE

OSPI_PHY_CONFIGURATION_REG BIT FIELD

DELAY VALUE

Transmit

1.8V

PHY_CONFIG_TX_DLL_DELAY_FLD

0x3E

3.3V

PHY_CONFIG_TX_DLL_DELAY_FLD

0x3B

Receive

1.8V, DQS

PHY_CONFIG_RX_DLL_DELAY_FLD

0x15

3.3V, DQS

PHY_CONFIG_RX_DLL_DELAY_FLD

0x3A

All other modes

PHY_CONFIG_RX_DLL_DELAY_FLD

0x0

AM6442, AM6441, AM6421, AM6412, AM6411

SPRSP56D – JANUARY 2021 – REVISED JULY 2022

www.ti.com

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