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AM6411...ALV 数据表(PDF) 197 Page - Texas Instruments |
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AM6411...ALV 数据表(HTML) 197 Page - Texas Instruments |
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197 / 244 page ![]() Table 7-111. PRU_ICSSG PRU Switching Characteristics – Shift Out Mode (continued) see Figure 7-95 NO. PARAMETER DESCRIPTION MIN MAX UNIT PRSO3 td(CLOCKOUT-DATAOUT) Delay time, CLOCKOUT to DATAOUT valid -1 4 ns (1) P = Software programmable shift out clock period, defined by PRUn_GPO_DIV0 and PRUn_GPO_DIV1 bit fields in the ICSSG_GPCFGn_REG register, where PRUn represents the respective PRU0 or PRU1 instance. (2) The Z parameter is defined as follows, where PRUn represents the respective PRU0 or PRU1 instance. a. If PRUn_GPI_DIV0 and PRUn_GPI_DIV1 are INTEGERS -or- if PRUn_GPI_DIV0 is a NON-INTEGER and PRUn_GPI_DIV1 is an EVEN INTEGER then, Z equals (PRUn_GPI_DIV0 * PRUn_GPI_DIV1). b. If PRUn_GPI_DIV0 is a NON-INTEGER and PRUn_GPI_DIV1 is an ODD INTEGER then, Z equals (PRUn_GPI_DIV0 * PRUn_GPI_DIV1 + 0.5). c. If PRUn_GPI_DIV0 is an INTEGER and PRUn_GPI_DIV1 is a NON-INTEGER then, Z equals (PRUn_GPI_DIV0 * PRUn_GPI_DIV1 + 0.5 * PRUn_GPI_DIV0). d. If PRUn_GPI_DIV0 and PRUn_GPI_DIV1 are NON-INTEGERS then, Z equals (PRUn_GPI_DIV0 * PRUn_GPI_DIV1 + 0.25 * PRUn_GPI_DIV0). (3) The Y parameter is defined as follows, where PRUn represents the respective PRU0 or PRU1 instance. a. If PRUn_GPI_DIV0 and PRUn_GPI_DIV1 are INTEGERS -or- if PRUn_GPI_DIV0 is a NON-INTEGER and PRUn_GPI_DIV1 is an EVEN INTEGER then, Y equals (PRUn_GPI_DIV0 * PRUn_GPI_DIV1). b. If PRUn_GPI_DIV0 is a NON-INTEGER and PRUn_GPI_DIV1 is an ODD INTEGER then, Y equals (PRUn_GPI_DIV0 * PRUn_GPI_DIV1 - 0.5). c. If PRUn_GPI_DIV0 is an INTEGER and PRUn_GPI_DIV1 is a NON-INTEGER then, Y equals (PRUn_GPI_DIV0 * PRUn_GPI_DIV1 - 0.5 * PRUn_GPI_DIV0). d. If PRUn_GPI_DIV0 and PRUn_GPI_DIV1 are NON-INTEGERS then, Y1 equals (PRUn_GPI_DIV0 * PRUn_GPI_DIV1 - 0.25 * PRUn_GPI_DIV0) and Y2 equals (PRUn_GPI_DIV0 * PRUn_GPI_DIV1 + 0.25 * PRUn_GPI_DIV0), where Y1 is the first high pulse and Y2 is the second high pulse. CLOCKOUT DATAOUT PRSO1 PRSO2H PRSO3 PRU_TIMING_06 PRSO2L Figure 7-95. PRU_ICSSG PRU Shift Out Timing 7.10.5.16.1.4 PRU_ICSSG PRU Sigma Delta and Peripheral Interface Table 7-112. PRU_ICSSG PRU Sigma Delta and Peripheral InterfaceTiming Conditions PARAMETER MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate 1 3 V/ns OUTPUT CONDITIONS CL Output load capacitance 2 18 pF 7.10.5.16.1.4.1 PRU_ICSSG PRU Sigma Delta and Peripheral Interface Timing Table 7-113. PRU_ICSSG PRU Timing Requirements – Sigma Delta Mode see Figure 7-96 and Figure 7-97 NO. PARAMETER DESCRIPTION MIN MAX UNIT PRSD1 tc(SD_CLK) Cycle time, SDx_CLK 40 ns PRSD2L tw(SD_CLKL) Pulse duration, SDx_CLK low 20 ns www.ti.com AM6442, AM6441, AM6421, AM6412, AM6411 SPRSP56D – JANUARY 2021 – REVISED JULY 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 197 Product Folder Links: AM6442 AM6441 AM6421 AM6412 AM6411 |
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