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For this example, it is important to understand which variables effect the maximum trigger threshold when

selecting resistor values. It is obvious a device which has a VMON_VSYS input threshold of 0.45 V + 3% needs

to be considered when trying to design a voltage divider that doesn’t trip until the system supply drops 10%. The

effect of resistor tolerance and input leakage also needs to be considered, but how these contributions effect

the maximum trigger point may not be obvious. When selecting component values which produce a maximum

trigger voltage, the system designer must consider a condition where the value of R1 is 1% low and the value of

R2 is 1% high combined with a condition where input leakage current for the VMON_VSYS pin is 2.5 µA. When

implementing a resistor divider where R1 = 4.81 KΩ and R2 = 40.2 KΩ, the result is a maximum trigger threshold

of 4.517 V.

Once component values have been selected to satisfy the maximum trigger voltage as described above, the

system designer can determine the minimum trigger voltage by calculating the applied voltage that produces an

output voltage of 0.45 V - 3% when the value of R1 is 1% high and the value of R2 is 1% low, and the input

leakage current is 10 nA, or zero. Using an input leakage of zero with the resistor values given above, the result

is a minimum trigger threshold of 4.013 V.

This example demonstrates a system power supply voltage trip point that ranges from 4.013 V to 4.517

V. Approximately 250 mV of this range is introduced by VMON_VSYS input threshold accuracy of ±3%,

approximately 150 mV of this range is introduced by resistor tolerance of ±1%, and approximately 100 mV

of this range is introduced by loading error when VMON_VSYS input leakage current is 2.5 µA.

The resistor values selected in this example produces approximately 100 µA of bias current through the resistor

divider when the system supply is 4.5 V. The 100 mV of loading error mentioned above could be reduced to

about 10 mV by increasing the bias current through the resistor divider to approximately 1 mA. So resistor

divider bias current vs loading error is something the system designer needs to consider when selecting

component values.

The system designer should also consider implementing a noise filter on the voltage divider output since

VMON_VSYS has minimum hysteresis and a high-bandwidth response to transients. This could be done by

installing a capacitor across R1 as shown in Figure 9-5. However, the system designer must determine the

response time of this filter based on system supply noise and expected response to transient events.

Device

VMON_VSYS

SPRSP56_VMON_ER_MON_01

VSS

4.81 k

Ω

40.2 k

Ω ±

VSYS

Value = Determined by system designer

(System Power Supply)

Figure 9-5. System Supply Monitor Voltage Divider Circuit

VMON_1P8_MCU and VMON_1P8_SOC pins provide a way to monitor external 1.8 V power supplies. These

pins should be connected directly to their respective power souce. An internal resistor divider with software

control is implemented inside the SoC for each of these pins. Software can program each internal resistor divider

to create appropriate under voltage and over voltage interrupts.

VMON_3P3_MCU and VMON_3P3_SOC pins provide a way to monitor external 3.3 V power supplies. These

pins should be connected directly to their respective power souce. An internal resistor divider with software

control is implemented inside the SoC for each of these pins. Software can program each internal resistor divider

to create appropriate under voltage and over voltage interrupts.

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AM6442, AM6441, AM6421, AM6412, AM6411

SPRSP56D – JANUARY 2021 – REVISED JULY 2022

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