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TL431IPG 数据表(PDF) 17 Page - ON Semiconductor |
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TL431IPG 数据表(HTML) 17 Page - ON Semiconductor |
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17 / 22 page ![]() TO−92 (TO−226) 1 WATT CASE 29−10 ISSUE D DATE 05 MAR 2021 STYLE 1: PIN 1. EMITTER 2. BASE 3. COLLECTOR STYLE 6: PIN 1. GATE 2. SOURCE & SUBSTRATE 3. DRAIN STYLE 11: PIN 1. ANODE 2. CATHODE & ANODE 3. CATHODE STYLE 16: PIN 1. ANODE 2. GATE 3. CATHODE STYLE 21: PIN 1. COLLECTOR 2. EMITTER 3. BASE STYLE 26: PIN 1. VCC 2. GROUND 2 3. OUTPUT STYLE 31: PIN 1. GATE 2. DRAIN 3. SOURCE STYLE 2: PIN 1. BASE 2. EMITTER 3. COLLECTOR STYLE 7: PIN 1. SOURCE 2. DRAIN 3. GATE STYLE 12: PIN 1. MAIN TERMINAL 1 2. GATE 3. MAIN TERMINAL 2 STYLE 17: PIN 1. COLLECTOR 2. BASE 3. EMITTER STYLE 22: PIN 1. SOURCE 2. GATE 3. DRAIN STYLE 27: PIN 1. MT 2. SUBSTRATE 3. MT STYLE 32: PIN 1. BASE 2. COLLECTOR 3. EMITTER STYLE 3: PIN 1. ANODE 2. ANODE 3. CATHODE STYLE 8: PIN 1. DRAIN 2. GATE 3. SOURCE & SUBSTRATE STYLE 13: PIN 1. ANODE 1 2. GATE 3. CATHODE 2 STYLE 18: PIN 1. ANODE 2. CATHODE 3. NOT CONNECTED STYLE 23: PIN 1. GATE 2. SOURCE 3. DRAIN STYLE 28: PIN 1. CATHODE 2. ANODE 3. GATE STYLE 33: PIN 1. RETURN 2. INPUT 3. OUTPUT STYLE 4: PIN 1. CATHODE 2. CATHODE 3. ANODE STYLE 9: PIN 1. BASE 1 2. EMITTER 3. BASE 2 STYLE 14: PIN 1. EMITTER 2. COLLECTOR 3. BASE STYLE 19: PIN 1. GATE 2. ANODE 3. CATHODE STYLE 24: PIN 1. EMITTER 2. COLLECTOR/ANODE 3. CATHODE STYLE 29: PIN 1. NOT CONNECTED 2. ANODE 3. CATHODE STYLE 34: PIN 1. INPUT 2. GROUND 3. LOGIC STYLE 5: PIN 1. DRAIN 2. SOURCE 3. GATE STYLE 10: PIN 1. CATHODE 2. GATE 3. ANODE STYLE 15: PIN 1. ANODE 1 2. CATHODE 3. ANODE 2 STYLE 20: PIN 1. NOT CONNECTED 2. CATHODE 3. ANODE STYLE 25: PIN 1. MT 1 2. GATE 3. MT 2 STYLE 30: PIN 1. DRAIN 2. GATE 3. SOURCE STYLE 35: PIN 1. GATE 2. COLLECTOR 3. EMITTER XXXX = Specific Device Code A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. GENERIC MARKING DIAGRAM* XXXXX XXXXX ALYWG G (Note: Microdot may be in either location) ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. 98AON52857E DOCUMENT NUMBER: DESCRIPTION: Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 3 OF 3 TO−92 (TO−226) 1 WATT © Semiconductor Components Industries, LLC, 2019 www.onsemi.com |
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